Flash memory

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Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. (Wikipedia.org)






Conferences related to Flash memory

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2013 15th International Conference on Advanced Communication Technology (ICACT)

Technology, standard, service, architecture, strategy, and policy in newly emerging systems and a variety of applications in the area of communications. ICACT2013 provides an open forum for scholar, researcher, engineer, policy maker, network planner, and service provider in the advanced communications technologies.


2012 IEEE 18th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2012)

Embedded and Real-Time Systems Ubiquitous Computing / Cyber-Physical Systems

  • 2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

    RTCSA will bring together researchers and developers from academia and industry for advancing the technology of embedded and real-time systems, and ubiquitous computing applications. The conference has the following goals: to investigate advances in embedded and real-time systems and ubiquitous computing applications; to promote interaction among the areas of embedded computing, real-time computing and ubiquitous computing; to evaluate the maturity and directions of embedded and real-time system and ubiquit


2011 IEEE 9th Symposium on Application Specific Processors (SASP)

Embedded processors cost and volume driven design. Domain-specific embedded processors, in markets such as network processing, automotive, and others, have splintered a pre-existing market for general-purpose, low-cost, low-energy processors.


2009 IEEE International Conference on Intelligent Computing and Intelligent Systems (ICIS 2009)

The scope of the conference includes, but not limited to AI, Artificial Life and Artificial Immune Systems, Cloud Computing, Computer Vision, Data Mining, Fuzzy System, Genetic Algorithms, Information Retrieval, Intelligent Control, Robotics, Machine Learning, Machine Translation, Neural Networks, Rough Set, Systems Biology, Video & Image Processing, etc.


2009 IEEE International Workshop on Memory Technology, Design and Testing (MTDT)

A forum dedicated to the recent advancements of the memory technology, covering topics such as memory device, circuit design, architecture, fabrication process, verification, yield analysis testing/diagnosis/repair for all kinds of memory.

  • 2007 IEEE International Workshop on Memory Technology, Design and Testing (MTDT)

    Following the traditions set up by its predecessors, MTDT07 will provide a forum dedicated to the recent advancements of the memory technology, covering topics such as memory device, circuit design, architecture, fabrication process, verification, yield analysis testing/diagnosis/repair for all kinds of memory such as SRAM, DRAM, Flash memory, EPROM, EEPROM, embedded memories, 3-D memories, content addressable memories, etc.



Periodicals related to Flash memory

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Magnetics, IEEE Transactions on

Science and technology related to the basic physics and engineering of magnetism, magnetic materials, applied magnetics, magnetic devices, and magnetic data storage. The Transactions publishes scholarly articles of archival value as well as tutorial expositions and critical reviews of classical subjects and topics of current interest.


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.




Xplore Articles related to Flash memory

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The design of the embedded digital controller

Guanglai Chen; Shoujun Wang; Lifei Li 2011 International Conference on Electric Information and Control Engineering, 2011

This paper describes the detailed design process and methods, which combines the using of embedded CPU with a special motion control chip embedded motion controller. Through the hardware platform design and software design of the embedded motion controller, it can know that the controller has some advantages, such as low cost, small size, low power consumption, feature-rich and stable characteristics. ...


Solid state disk: A new storage device for video storage server

Amir Rizaan Rahiman; Putra Sumari 2008 International Symposium on Information Technology, 2008

Solid state disk (SSD) is a new storage device that utilizes semiconductor memory chips (e.g. RAM, EEPROM, flash memory) to store data rather than using conventional spinning platters and moving heads found in conventional magnetic disk drive. The term of "solid state" means there are no moving parts involve in accessing, storing and retrieving required data on the drive. Several ...


Design of Transient Recorder Based on USB 2.0

Ying-lian Li; Bing Hu 2010 International Conference on Electrical and Control Engineering, 2010

The paper developed an transient recorder based on USB2.0 interface. It makes full use of the high-speed transfer capability of USB chips and FPGA technology to achieve high-speed acquisition for transient signal in the offline state, and uses FLASH memory to store the large-capacity data. At the same time, the instrument uses the power supply circuit of sensor to supply ...


Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration

Woo Young Choi; Hei Kam; Donovan Lee; Joanna Lai; Tsu-Jae King Liu 2007 IEEE International Electron Devices Meeting, 2007

A new electro-mechanical non-volatile memory (NVM) cell design is proposed and demonstrated for the first time. The fabricated cells operate with relatively low program/erase voltages and large sensing margin. Because only dielectric and metal layers are required, this cell design is suitable for post-CMOS fabrication. As the cell area is reduced, low operating voltages can be maintained by scaling the ...


Robust shallow trench isolation technique used for 75nm nor flash memory

Jeng-Hwa Liao; Kuo-Liang Wei; Hong-Ji Lee; Chun-Min Cheng; Chun-Ling Chiang; Jung-Yu Hsieh; Ling-Wu Yang; Tahone Yang; Kuang-Chao Chen; Chih-Yuan Lu 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2010

We have developed a new Self-aligned poly (SAP) process to improve the tunnel oxide integrity by optimizing the shallow trench isolation (STI) corner rounding profile and reducing the local oxide thinning effect. It is found that double in-situ steam generation (ISSG) liner oxides can effectively improve the STI corner rounding. As for the local oxide thinning effect, the composite pad ...


More Xplore Articles

Educational Resources on Flash memory

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eLearning

The design of the embedded digital controller

Guanglai Chen; Shoujun Wang; Lifei Li 2011 International Conference on Electric Information and Control Engineering, 2011

This paper describes the detailed design process and methods, which combines the using of embedded CPU with a special motion control chip embedded motion controller. Through the hardware platform design and software design of the embedded motion controller, it can know that the controller has some advantages, such as low cost, small size, low power consumption, feature-rich and stable characteristics. ...


Solid state disk: A new storage device for video storage server

Amir Rizaan Rahiman; Putra Sumari 2008 International Symposium on Information Technology, 2008

Solid state disk (SSD) is a new storage device that utilizes semiconductor memory chips (e.g. RAM, EEPROM, flash memory) to store data rather than using conventional spinning platters and moving heads found in conventional magnetic disk drive. The term of "solid state" means there are no moving parts involve in accessing, storing and retrieving required data on the drive. Several ...


Design of Transient Recorder Based on USB 2.0

Ying-lian Li; Bing Hu 2010 International Conference on Electrical and Control Engineering, 2010

The paper developed an transient recorder based on USB2.0 interface. It makes full use of the high-speed transfer capability of USB chips and FPGA technology to achieve high-speed acquisition for transient signal in the offline state, and uses FLASH memory to store the large-capacity data. At the same time, the instrument uses the power supply circuit of sensor to supply ...


Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration

Woo Young Choi; Hei Kam; Donovan Lee; Joanna Lai; Tsu-Jae King Liu 2007 IEEE International Electron Devices Meeting, 2007

A new electro-mechanical non-volatile memory (NVM) cell design is proposed and demonstrated for the first time. The fabricated cells operate with relatively low program/erase voltages and large sensing margin. Because only dielectric and metal layers are required, this cell design is suitable for post-CMOS fabrication. As the cell area is reduced, low operating voltages can be maintained by scaling the ...


Robust shallow trench isolation technique used for 75nm nor flash memory

Jeng-Hwa Liao; Kuo-Liang Wei; Hong-Ji Lee; Chun-Min Cheng; Chun-Ling Chiang; Jung-Yu Hsieh; Ling-Wu Yang; Tahone Yang; Kuang-Chao Chen; Chih-Yuan Lu 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2010

We have developed a new Self-aligned poly (SAP) process to improve the tunnel oxide integrity by optimizing the shallow trench isolation (STI) corner rounding profile and reducing the local oxide thinning effect. It is found that double in-situ steam generation (ISSG) liner oxides can effectively improve the STI corner rounding. As for the local oxide thinning effect, the composite pad ...


More eLearning Resources

IEEE-USA E-Books

  • Principle of Nand Flash Memory

    This chapter shows the single-cell architecture of NAND flash memory. One NAND string consists of 32 series-connected stacked gate memory transistors and two select gate transistors. The scaling of a high-voltage transistor (HV Tr) is one of the important challenges for NAND flash memories. Several program and erase schemes were considered to use a NAND flash memory product in early stage of development. There are several program boosting schemes for multilevel NAND flash cells. The first one is a conventional selfboosting (SB) scheme. The second one is a local self-boosting scheme. The third one is the erase-area self-boosting scheme (EASB). EASB was widely used for multilevel cell (MLC) to obtain a higher boosting voltage. In order to relax high electric field, the self-boosting scheme is becoming a more advanced and complicated scheme for each generation of NAND flash memory.

  • Three-Dimensional Nand Flash Cell

    This chapter introduces major three-dimensional (3D) cells. The bit cost scalable (BiCS) cell has a new structure of the stacked control gate layers and vertical poly-silicon channel. The thinner poly-silicon channel can obtain the easier electrostatic control performed by the gate electrode over the thinner body and the smaller poly-silicon grains which reduce the impact on the channel current of statistical variation of smaller grain size configuration. Terabit cell array transistor (TCAT) has a similar structure of BiCS, with a vertical poly-silicon channel, stacked word lines, and a silicon nitride (SiN) charge storage layer of the surrounding gate SONOS cell. The chapter describes a process sequence of vertical gate NAND (VG-NAND) cell and proposes a dual control gate with a surrounding floating-gate (DC-SF) cell for 3D NAND flash memory. This structure allows to apply floating gate to a 3D stacked cell structure with minimal cell size and high coupling ratio.

  • Nand Flash Memory Devices

    The most important requirement for NAND flash memory is a low bit cost. This chapter discusses the NAND flash memory cell and its scaling technologies. Requirements for isolation in NAND flash memory cell are more severe than other devices due to high-voltage operation during programming. Therefore, it was difficult to scale down of local oxidation of silicon (LOCOS) isolation width beyond 1.5-m width due to boron diffusion from isolation bottom by LOCOS oxidation process. Then, a new field through implantation (FTI) process was developed. Next, the self-aligned shallow trench isolation cell (SA-STI cell) with floating gate (FG) wing had been developed. The chapter presents the planar FG cell and also discusses the side wall transfer-transistor (SWATT) cell as alternate memory cell technology for a multilevel NAND flash memory cell. Finally, it presents other advanced NAND flash device technologies.

  • Prospects and Challenges of NextGeneration Flash Memory Devices

    This chapter contains sections titled: Introduction Scaling challenges Technological innovations Conclusions

  • Embedded Flash Memory

    This chapter contains sections titled: Introduction Embedded Flash Versus Stand-Alone Flash Memory Embedded Flash Memory Applications Embedded Flash Memory Cells Embedded Flash Memory Design References

  • ARM?? Microcontroller Memory System

    This chapter provides general information about the ARM ?? Cortex ?? -M4 microcontroller memory system. The discussion is mainly concentrated on the memory system used in the TM4C123GH6PM MCU system. The chapter includes the system memory map specially designed for the TM4C123GH6PM MCU, connections between the processor and memory, and the connection between the memory and peripherals, memory architecture and requirements, bit-band principle and operations, memory access attributes, memory endianness, memory access behaviors, and memory programming applications in TM4C123GH6PM MCU system. The memory devices discussed in the chapter includes Static random-access memory (SRAM) (32 KB), Flash Memory (256 KB), Internal ROM and Electrically Erasable Programmable ROM (EEPROM) (2 KB). In order to access and control 4-GB memory space effectively and easily, the entire 4-GB memory space in the Cortex ?? -M4 system is divided into the different regions for various predefined memory and peripheral devices uses.

  • Advanced Nonvolatile Memory Designs and Technologies

    This chapter contains sections titled: Nonvolatile Memory Advances Floating Gate Cell Theory and Operations Nonvolatile Memory Cell and Array Designs Flash Memory Architectures Multilevel Nonvolatile Memories Flash Memory Reliability Issues Ferroelectric Memories This chapter contains sections titled: References

  • Challenges Of Three-Dimensional Nand Flash Memory

    This chapter introduces several types of three-dimensional (3D) NAND flash memory cells. It first addresses the challenges of 3D NAND flash memory and discusses data retention issues. The data retention characteristic of SONOS cell has problems of quick charge loss and large Vt shift in retention bake because of charge detrapping through thinner tunnel oxide. The chapter presents the analysis results of program disturb in 3D NAND cells. The program disturb mechanisms of 3D NAND cells are much different from that of 2D NAND cells, because cell structure and array architecture are totally changed. The cell current is much decreased in the 3D NAND cell, because channel material is changed from crystal Si (substrate Si) to poly-Si. The chapter describes the new structure of the peripheral circuit under cell array. Finally, it discusses the future trend of the 3D NAND cell.

  • Advanced Operation for Multilevel Cell

    The multilevel cell (MLC) technology was initially developed for MLC (2 bits/cell), but it was extended to TLC (3 bits/cell) and QLC (4 bits/cell). MLC technology has been developed to focus on the operations of making narrow Vt distribution width. A lot of sophisticated techniques have been proposed and implemented to a NAND flash memory product. This chapter first describes these techniques, such as the incremental step pulse program (ISPP), bit-by- bit verify operations, a two-step verify scheme, and a pseudo-pass scheme. It then discusses several page program sequences to reduce the effect of floating-gate capacitive coupling. The chapter also describes TLC (3 bits/cell) and QLC (4 bits/cell) technologies. Next, the three-level cell technology is introduced to compromise the performance and reliability of single-level cell (SLC) and MLC. Finally, the moving read algorithm is presented to compensate a Vt shift for minimizing a bit failure rate.

  • Tunnel Dielectrics for Scaled Flash Memory Cells

    This chapter contains sections titled: Introduction SiO2 as Tunnel Dielectric - Historical Perspective Early Work on Silicon Nitride as a Tunnel Dielectric Jet-Vapor Deposition Silicon Nitride Deposition Properties of Gate-Quality JVD Silicon Nitride Films Deposited Silicon Nitride as Tunnel Dielectric N-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric P-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric Reliability Concerns Associated with Hot-Hole Injection Tunnel Dielectric for SONOS Cell Prospects for High-K Dielectrics Tunnel Barrier Engineering with Multiple Barriers Summary References



Standards related to Flash memory

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