eLearning

Gordon: An Improved Architecture for Data-Intensive Applications

Adrian M. Caulfield; Laura M. Grupp; Steven Swanson IEEE Micro, 2010

Gordon is a system architecture for data-centric applications combining low- power processors, flash memory, and data-centric programming systems to improve performance and efficiency for data-centric applications, the article explores the Gordon design space and the design of a specialized flash translation layer. Gordon systems can outperform disk-based clusters by 1.5x and deliver 2.5x more performance per watt.

A novel p-channel NAND-type flash memory with 2-bit/cell operation and high programming throughput (> 20 MB/sec)

Hang-Ting Lue; Szu-Yu Wang; Erh-Kun Lai; Min-Ta Wu; Ling-Wu Yang; Kuang-Chao Chen; J. Ku; Kuang-Yeu Hsieh; R. Liu; Chih-Yuan Lu IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005

A novel p-channel NAND-type non-volatile flash memory using nitride-trapping device is presented. The p-channel device is programmed by very efficient band-to-band tunneling hot electron (BBHE), and erased by self-converging channel hole tunneling. An ultra-thin bandgap engineered ONO tunneling dielectric as presented in H. T. Lue et al. (2005) is adopted to achieve efficient hole-tunneling erase at high electric field, but ...

40 V high voltage arbitrary waveform pulse generator at automatic parametric tester

Yang Pan; James Yu; Jay Kim; Peter Griffiths 2007 International Semiconductor Device Research Symposium, 2007

This paper introduces the development work of high voltage pulse capability of Keithley automatic parametric tester (APT). To meet the market demand for high voltage (40 V) function/arbitrary waveform pulse generator, Keithley Instruments developed new pulse generator that implements both features of high voltage and function/arbitrary pulse waveform within single instrument. Integrated this new pulse generator into APT, provides flash ...

Alpha-induced soft errors in Floating Gate flash memories

M. Bagatin; S. Gerardin; A. Paccagnella; V. Ferlet-Cavrois 2012 IEEE International Reliability Physics Symposium (IRPS), 2012

We study the sensitivity to alpha particles of state-of-the-art Multi-Level Cell (MLC) and Single-Level Cell (SLC) NAND Floating Gate (FG) flash memories with NAND architecture. We show that starting from a feature size of 50 nm, MLC flash memories are sensitive to alpha particles, whereas SLC devices do not show any sensitivity down to a feature size of 34 nm. ...

An Experimental 1Mb 0.11um 4.5F2 1.8Volt Multilevel Vertical Split Gate Source Side Injection Test Vehicle for Giga-Bit Density NOR Flash Memory

Hieu Van Tran; Anh Ly; Vishal Sarin; Sang T. Nguyen; Hung Q. Nguyen; Loc Hoang; Hyun Bai Kim; Isao Nojima; Dana Lee; Bomy Chen 2005 IEEE Asian Solid-State Circuits Conference, 2005

An experimental 0.11mum 4.5F2 1.8V multilevel 1Mb vertical floating gate split gate source side injection (SSI) test vehicle for Giga-bit NOR flash memory is shown for the first time. Novel coupled sense line programming for 25mV precise charge placement and novel low cell current ~10ua mode source follower sense amplifier is shown to enable high speed high density G-bit MLC ...

IEEE-USA E-Books

• Reliability Of Nand Flash Memory

  Reliability of NAND flash memory is more interesting than that of other semiconductor devices. Program and erase of NAND flash perform by electron injection and emission to/from floating gate (FG). There are several methods of electron injection and emission. For electron injection, there are two methods, namely channel hot electron (CHE) injection and Fowler-Nordheim tunneling (FN-t) injection. Data retention is degraded by electron and hole traps in tunnel oxide. Detrapping of trapped charges in tunnel oxide is a major root cause of Vt shift during the data retention test. Read disturb failure is mainly caused in the erase state after program/erase cycling stress. The stress-induced leakage current (SILC), which is generated by program/erase cycling stress, is major root cause for the read-disturb phenomena. The mechanism of erratic over program is considered to be an excess electron injection at hole trap sites in tunnel oxide.

• Physics of Flash Memories

  This chapter contains sections titled: Introduction Basic Operating Principles and Memory Characteristics Physics of Programming and Erase Mechanisms Physics of Degradation and Disturb Mechanisms Conclusion References

• Three-Dimensional Nand Flash Cell

  This chapter introduces major three-dimensional (3D) cells. The bit cost scalable (BiCS) cell has a new structure of the stacked control gate layers and vertical poly-silicon channel. The thinner poly-silicon channel can obtain the easier electrostatic control performed by the gate electrode over the thinner body and the smaller poly-silicon grains which reduce the impact on the channel current of statistical variation of smaller grain size configuration. Terabit cell array transistor (TCAT) has a similar structure of BiCS, with a vertical poly-silicon channel, stacked word lines, and a silicon nitride (SiN) charge storage layer of the surrounding gate SONOS cell. The chapter describes a process sequence of vertical gate NAND (VG-NAND) cell and proposes a dual control gate with a surrounding floating-gate (DC-SF) cell for 3D NAND flash memory. This structure allows to apply floating gate to a 3D stacked cell structure with minimal cell size and high coupling ratio.

• NOR Flash Stacked and SplitGate Memory Technology

  This chapter contains sections titled: Introduction ETOX Flash Cell Technology SST SuperFlash EEPROM Cell Technology Reliability Issues and Solutions Applications References

• Challenges Of Three-Dimensional Nand Flash Memory

  This chapter introduces several types of three-dimensional (3D) NAND flash memory cells. It first addresses the challenges of 3D NAND flash memory and discusses data retention issues. The data retention characteristic of SONOS cell has problems of quick charge loss and large Vt shift in retention bake because of charge detrapping through thinner tunnel oxide. The chapter presents the analysis results of program disturb in 3D NAND cells. The program disturb mechanisms of 3D NAND cells are much different from that of 2D NAND cells, because cell structure and array architecture are totally changed. The cell current is much decreased in the 3D NAND cell, because channel material is changed from crystal Si (substrate Si) to poly-Si. The chapter describes the new structure of the peripheral circuit under cell array. Finally, it discusses the future trend of the 3D NAND cell.

• Front Matter

  The prelims comprise: Half Title EpiGraph Title Copyright Contents Foreword Preface Acknowledgments About the Author

• NAND Flash Memory Technology

  This chapter contains sections titled: Overview of NAND EEPROM NAND Cell Operation NAND Array Architecture and Operation Program Threshold Control and Program Vt Spread Reduction Process and Scaling Issues Key Circuits and Circuit/Technology Interactions Multilevel NAND References Bibliography

• Conclusions

  The development of NAND flash memory started in 1987 in the R&D center of Toshiba Corporation. The target market was the replacement of magnetic memory, such as HDD, and so on. The first NAND flash memory cells of 1-m rule was8*F2 cell size by using a wide x-direction pitch of 4 m (4*F) because LOCOS isolation width was 3 m wide due to the limitation of the high-voltage operation. The reasons why the NAND flash memory was accepted to the emerging applications were a low bit cost, high reliability, high performance, and low power consumption. The power consumption of storage memory has been greatly reduced by using NAND flash memory, compared with magnetic memory of HDD. In the data center, SSD based on NAND flash memory can reduce the power consumption of an enterprise server, and replace HDD, because of low power operation in NAND flash memory and low cooling power.

• Introduction

  A breakthrough in the field of nonvolatile memories was the invention of the flash memory, which is a new type of electrically erasable and programmable read-only memory (EEPROM). Flash memory application can be classified into two major markets. One is for code storage applications, such as PC BIOS, cellular phones, and DVDs. The NOR-type cell is best suitable for this market due to its fast random access speed. The other is for file storage applications, such as the digital still camera (DSC), silicon audio, the smartphone, and the tablet PC. The NAND-type cell is suitable for file storage market. NAND flash has become an explosive innovation and has greatly contributed to the improvement of the lives with the advent of convenient mobile equipment such as smartphones and tablet PCs. Data retention time after programming and erase cycling is a key of NAND flash reliability.

• DINOR Flash Memory Technology

  This chapter contains sections titled: Introduction DINOR Operation and Array Architecture DINOR Technology Features DINOR Circuit for Low-Voltage Operation Background Operation Function P-Channel DINOR Architecture References Bibliography