Flash memory

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Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. (Wikipedia.org)






Conferences related to Flash memory

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2020 Joint Conference of the IEEE International Frequency Control Symposium and International Symposium on Applications of Ferroelectrics (IFCS-ISAF)

Ferroelectric materials and applications


2019 IEEE 11th International Memory Workshop (IMW)

The IMW is a unique forum for specialists in all aspects of memory (nonvolatile & volatile)microelectronics and people with different backgrounds who wish to gain a better understandingof the field. The morning and afternoon technical sessions are organized in a manner thatprovides ample time for informal exchanges amongst presenters and attendees. The eveningpanel discussions will address hot topics in the memory and memory system field. Papers aresolicited in all aspects of semiconductor memory technology (Flash, DRAM, SRAM, PCRAM,RRAM, MRAM, embedded memory, and other NV memories).


2019 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


2019 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


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Periodicals related to Flash memory

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Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Components and Packaging Technologies, IEEE Transactions on

Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.


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Xplore Articles related to Flash memory

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Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

IEEE Electron Device Letters, 1999

The effects of the substrate bias on the characteristics of split-gate EEPROM/Flash memory cells have been investigated. It is experimentally demonstrated that applying negative substrate bias (NSB) can improve the programming and erasing speed significantly. The improvements can be attributed that NSB effectively increase the needed electrical fields for fast programming and erasing, respectively. Furthermore, the cycling endurance is improved ...


A 3.42 /spl mu/m/sup 2/ Flash Memory Cell Technology Conformable to a Sector Erase

1991 Symposium on VLSI Technology, 1991

None


Split-gate NAND flash memory at 120nm technology node featuring fast programming and erase

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 2004

For the first time, split-gate NAND flash memory featuring interpoly erase and mid-channel programming is demonstrated at 120nm technology node. The cell array operates at single polarity voltages lower than 12V. Erase and programming can be accomplished in 0.5ms and 10/spl mu/s, respectively.


Stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics

IEEE Transactions on Electron Devices, 1998

This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (/spl Delta/V/sub th/) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region ...


Observations of single electron trapping/detrapping events in tunnel oxide of SuperFlash/spl trade/ memory cell

Proceedings. 2004 IEEE Computational Systems Bioinformatics Conference, 2004

Erase instabilities and erase performance degradation due to single-electron trapping events in tunnel oxide of SST split-gate SuperFlash/spl trade/ memory cells have been detected and analyzed for the first time. Whereas the instabilities of erase characteristics in stacked-gate flash memories ("erratic erase") are attributed to hole trapping/detrapping associated with anode hole injection, SuperFlash/spl trade/ cell does not show any hole- ...


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Educational Resources on Flash memory

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IEEE-USA E-Books

  • Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

    The effects of the substrate bias on the characteristics of split-gate EEPROM/Flash memory cells have been investigated. It is experimentally demonstrated that applying negative substrate bias (NSB) can improve the programming and erasing speed significantly. The improvements can be attributed that NSB effectively increase the needed electrical fields for fast programming and erasing, respectively. Furthermore, the cycling endurance is improved considerably if NSB is applied for programming and erasing operation both.

  • A 3.42 /spl mu/m/sup 2/ Flash Memory Cell Technology Conformable to a Sector Erase

    None

  • Split-gate NAND flash memory at 120nm technology node featuring fast programming and erase

    For the first time, split-gate NAND flash memory featuring interpoly erase and mid-channel programming is demonstrated at 120nm technology node. The cell array operates at single polarity voltages lower than 12V. Erase and programming can be accomplished in 0.5ms and 10/spl mu/s, respectively.

  • Stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics

    This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (/spl Delta/V/sub th/) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region is due to both the initial trapping or detrapping of the carriers in the tunnel oxide and the decay of the stress-induced leakage current of the tunnel oxide. The steady-state region is determined by the saturation of the stress-induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady-state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high- temperature (125/spl deg/C) write/erase operation degrades the steady-state region characteristics in comparison with room temperature (30/spl deg/C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures.

  • Observations of single electron trapping/detrapping events in tunnel oxide of SuperFlash/spl trade/ memory cell

    Erase instabilities and erase performance degradation due to single-electron trapping events in tunnel oxide of SST split-gate SuperFlash/spl trade/ memory cells have been detected and analyzed for the first time. Whereas the instabilities of erase characteristics in stacked-gate flash memories ("erratic erase") are attributed to hole trapping/detrapping associated with anode hole injection, SuperFlash/spl trade/ cell does not show any hole- related processes in tunnel oxide. A different behavior of SuperFlash/spl trade/ cell compared to conventional stacked-gate cell during erase operation due to different cell structures has been analyzed.

  • Stacked gate mid-channel injection flash EEPROM cell. I. Programming speed and efficiency versus device structure

    Presents a new flash EEPROM cell which has been fabricated to achieve fast programming with low power. This memory cell attains speed and efficiency, comparable to the split-gate device, while preserving a simple stacked gate structure. The device programs faster than the stacked gate cell by a factor of about ten. Also, the threshold voltage shift of 5 V can be accomplished with the drain voltage of 3 V in about 50 /spl mu/s. The proposed memory cell is strongly resistant against the punchthrough effect and is capable of erasure in byte unit at the drain side. Factors pertinent to programming are discussed, theoretically and experimentally, in correlation with device structures. The hot electron dwell time in the channel is shown to be an important parameter, affecting the programming speed and efficiency.

  • Measurement system for a preliminary characterization of flash memory cells for multilevel applications

    In this work a low-cost measurement system suitable for analog characterization of standard Flash memory cells is presented. Our aim, with this system, is to investigate the possibility of using standard cells for multilevel storage, to increase the bit density of conventional memory devices. Preliminary investigation was carried out by using a measurement system based on stand-alone instrumentation linked to a controller via IEEE 488 bus. The preliminary characterization results of the Texas Instruments TMS29FO40 4-Mbit Flash Memory show that it is feasible to store and retrieve information with four levels of injection charge in a single cell. Currently, a first multilevel test chip is under development. At the same time, a new measurement system, specifically suited to debug and test this special device, is under implementation.

  • Detailed observation of small leak current in flash memories with thin tunnel oxides

    This paper describes a method for measuring the small current through the oxides on the order of 10/sup -20/ A or less using a floating gate MOSFET and the application results on flash memories with thin tunnel oxides. The method is based on an accurate measurement of the threshold voltage of a floating gate MOSFET with no charge in the floating gate. We applied this method to flash memories to investigate the leak current behavior through thin tunnel oxides with very small areas (<0.16 /spl mu/m/sup 2/), and found some anomalous phenomena which cannot be observed from SILC measurements if we use large capacitors. We also discuss possible mechanisms to explain the phenomena.

  • On the cell misalignment for multilevel storage FLASH E/sup 2/PROM

    This paper presents for the first time the manufacturing issues due to cell misalignment encountered in multilevel FLASH memories. Split gate memory cells in mirrored pairs show varied program efficiency upon less ideal alignment, where device with a shorter Lsg has a poorer efficiency. This misalignment adversely impacts the dynamic range of the storage levels.

  • A simple and efficient self-limiting erase scheme for high performance split-gate flash memory cells

    This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells.



Standards related to Flash memory

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No standards are currently tagged "Flash memory"