Flash memory

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Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. (Wikipedia.org)

Conferences related to Flash memory

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2020 Joint Conference of the IEEE International Frequency Control Symposium and International Symposium on Applications of Ferroelectrics (IFCS-ISAF)

Ferroelectric materials and applications

2019 IEEE 11th International Memory Workshop (IMW)

The IMW is a unique forum for specialists in all aspects of memory (nonvolatile & volatile)microelectronics and people with different backgrounds who wish to gain a better understandingof the field. The morning and afternoon technical sessions are organized in a manner thatprovides ample time for informal exchanges amongst presenters and attendees. The eveningpanel discussions will address hot topics in the memory and memory system field. Papers aresolicited in all aspects of semiconductor memory technology (Flash, DRAM, SRAM, PCRAM,RRAM, MRAM, embedded memory, and other NV memories).

2019 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.

2019 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.

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Periodicals related to Flash memory

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Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...

Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)

Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...

Components and Packaging Technologies, IEEE Transactions on

Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.

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Xplore Articles related to Flash memory

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Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

[{u'author_order': 1, u'affiliation': u'Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37290267500', u'full_name': u'Kuo-Ching Huang', u'id': 37290267500}, {u'author_order': 2, u'authorUrl': u'https://ieeexplore.ieee.org/author/37281337200', u'full_name': u'Yean-Kuen Fang', u'id': 37281337200}, {u'author_order': 3, u'authorUrl': u'https://ieeexplore.ieee.org/author/37283323200', u'full_name': u'Dun-Nian Yaung', u'id': 37283323200}, {u'author_order': 4, u'authorUrl': u'https://ieeexplore.ieee.org/author/37367493900', u'full_name': u'Chii-Wen Chen', u'id': 37367493900}, {u'author_order': 5, u'authorUrl': u'https://ieeexplore.ieee.org/author/37275278600', u'full_name': u'Hung-Cheng Sung', u'id': 37275278600}, {u'author_order': 6, u'authorUrl': u'https://ieeexplore.ieee.org/author/37376260000', u'full_name': u'Di-Son Kuo', u'id': 37376260000}, {u'author_order': 7, u'authorUrl': u'https://ieeexplore.ieee.org/author/37280017000', u'full_name': u'C.S. Wang', u'id': 37280017000}, {u'author_order': 8, u'authorUrl': u'https://ieeexplore.ieee.org/author/37277069500', u'full_name': u'Mong-Song Liang', u'id': 37277069500}] IEEE Electron Device Letters, 1999

The effects of the substrate bias on the characteristics of split-gate EEPROM/Flash memory cells have been investigated. It is experimentally demonstrated that applying negative substrate bias (NSB) can improve the programming and erasing speed significantly. The improvements can be attributed that NSB effectively increase the needed electrical fields for fast programming and erasing, respectively. Furthermore, the cycling endurance is improved ...

A 3.42 /spl mu/m/sup 2/ Flash Memory Cell Technology Conformable to a Sector Erase

[{u'author_order': 1, u'affiliation': u'Hitachi Device Engineering Co., Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37264897200', u'full_name': u'H. Kume', u'id': 37264897200}, {u'author_order': 2, u'authorUrl': u'https://ieeexplore.ieee.org/author/37349031000', u'full_name': u'T. Tanaka', u'id': 37349031000}, {u'author_order': 3, u'authorUrl': u'https://ieeexplore.ieee.org/author/37345566800', u'full_name': u'T. Adachi', u'id': 37345566800}, {u'author_order': 4, u'authorUrl': u'https://ieeexplore.ieee.org/author/37346387400', u'full_name': u'N. Miyamoto', u'id': 37346387400}, {u'author_order': 5, u'authorUrl': u'https://ieeexplore.ieee.org/author/37264876200', u'full_name': u'S. Saeki', u'id': 37264876200}, {u'author_order': 6, u'authorUrl': u'https://ieeexplore.ieee.org/author/37264999300', u'full_name': u'Y. Ohji', u'id': 37264999300}, {u'author_order': 7, u'authorUrl': u'https://ieeexplore.ieee.org/author/37353794300', u'full_name': u'M. Ushiyama', u'id': 37353794300}, {u'author_order': 8, u'authorUrl': u'https://ieeexplore.ieee.org/author/37277784500', u'full_name': u'T. Kobayashi', u'id': 37277784500}, {u'author_order': 9, u'authorUrl': u'https://ieeexplore.ieee.org/author/37344729800', u'full_name': u'T. Nishida', u'id': 37344729800}, {u'author_order': 10, u'authorUrl': u'https://ieeexplore.ieee.org/author/37338982800', u'full_name': u'Y. Kawamoto', u'id': 37338982800}, {u'author_order': 11, u'authorUrl': u'https://ieeexplore.ieee.org/author/37350943900', u'full_name': u'K. Seki', u'id': 37350943900}] 1991 Symposium on VLSI Technology, 1991


Split-gate NAND flash memory at 120nm technology node featuring fast programming and erase

[{u'author_order': 1, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37276773400', u'full_name': u'Cheng-Yuan Hsu', u'id': 37276773400}, {u'author_order': 2, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37275673400', u'full_name': u'Chi-Wei Hung', u'id': 37275673400}, {u'author_order': 3, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37276225800', u'full_name': u'Da Sung', u'id': 37276225800}, {u'author_order': 4, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37276428300', u'full_name': u'Chi-Shan Wu', u'id': 37276428300}, {u'author_order': 5, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37065815000', u'full_name': u'S.C. Chen', u'id': 37065815000}, {u'author_order': 6, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37269874800', u'full_name': u'H.H. Kuo', u'id': 37269874800}, {u'author_order': 7, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37277291100', u'full_name': u'J.Y. Pan', u'id': 37277291100}, {u'author_order': 8, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37280745600', u'full_name': u'C.L. Chen', u'id': 37280745600}, {u'author_order': 9, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37264989400', u'full_name': u'I.C. Chuang', u'id': 37264989400}, {u'author_order': 10, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37264978200', u'full_name': u'V. Huang', u'id': 37264978200}, {u'author_order': 11, u'affiliation': u'PowerChip Semicond. Corp., Hsin-Chu, Taiwan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37264986200', u'full_name': u'C.C. Hsue', u'id': 37264986200}, {u'author_order': 12, u'authorUrl': u'https://ieeexplore.ieee.org/author/37264987300', u'full_name': u'D.-T. Fan', u'id': 37264987300}, {u'author_order': 13, u'authorUrl': u'https://ieeexplore.ieee.org/author/37278639500', u'full_name': u'Jung-Chang Lu', u'id': 37278639500}, {u'author_order': 14, u'authorUrl': u'https://ieeexplore.ieee.org/author/38255178200', u'full_name': u'C.Y.-S. Cho', u'id': 38255178200}, {u'author_order': 15, u'authorUrl': u'https://ieeexplore.ieee.org/author/37276123200', u'full_name': u'K. Tseng', u'id': 37276123200}, {u'author_order': 16, u'authorUrl': u'https://ieeexplore.ieee.org/author/37271985400', u'full_name': u'A. Hsu', u'id': 37271985400}, {u'author_order': 17, u'authorUrl': u'https://ieeexplore.ieee.org/author/37264992700', u'full_name': u'B. Sheen', u'id': 37264992700}, {u'author_order': 18, u'authorUrl': u'https://ieeexplore.ieee.org/author/37264992400', u'full_name': u'P. Tuntasood', u'id': 37264992400}, {u'author_order': 19, u'authorUrl': u'https://ieeexplore.ieee.org/author/37280745700', u'full_name': u'Chiou-Feng Chen', u'id': 37280745700}] Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 2004

For the first time, split-gate NAND flash memory featuring interpoly erase and mid-channel programming is demonstrated at 120nm technology node. The cell array operates at single polarity voltages lower than 12V. Erase and programming can be accomplished in 0.5ms and 10/spl mu/s, respectively.

Stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics

[{u'author_order': 1, u'affiliation': u'Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37342008000', u'full_name': u'S. Satoh', u'id': 37342008000}, {u'author_order': 2, u'authorUrl': u'https://ieeexplore.ieee.org/author/37352299000', u'full_name': u'G. Hemink', u'id': 37352299000}, {u'author_order': 3, u'authorUrl': u'https://ieeexplore.ieee.org/author/37338863200', u'full_name': u'K. Hatakeyama', u'id': 37338863200}, {u'author_order': 4, u'authorUrl': u'https://ieeexplore.ieee.org/author/37352316400', u'full_name': u'S. Aritome', u'id': 37352316400}] IEEE Transactions on Electron Devices, 1998

This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (/spl Delta/V/sub th/) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region ...

Observations of single electron trapping/detrapping events in tunnel oxide of SuperFlash/spl trade/ memory cell

[{u'author_order': 1, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37938026800', u'full_name': u'Y. Tkachev', u'id': 37938026800}, {u'author_order': 2, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37935039800', u'full_name': u'Xian Liu', u'id': 37935039800}, {u'author_order': 3, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37301973000', u'full_name': u'A. Kotov', u'id': 37301973000}, {u'author_order': 4, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37925799600', u'full_name': u'V. Markov', u'id': 37925799600}, {u'author_order': 5, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'authorUrl': u'https://ieeexplore.ieee.org/author/37432841800', u'full_name': u'A. Levi', u'id': 37432841800}] Proceedings. 2004 IEEE Computational Systems Bioinformatics Conference, 2004

Erase instabilities and erase performance degradation due to single-electron trapping events in tunnel oxide of SST split-gate SuperFlash/spl trade/ memory cells have been detected and analyzed for the first time. Whereas the instabilities of erase characteristics in stacked-gate flash memories ("erratic erase") are attributed to hole trapping/detrapping associated with anode hole injection, SuperFlash/spl trade/ cell does not show any hole- ...

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  • Nanomanufacturing for Electronics or Optoelectronics

    Artefacts in widespread use in electronic and optoelectronic systems have been manufactured by low‐cost, high‐volume processes. This chapter reviews recent progress and lack of progress on manufacturability of several nanoscale systems using the criteria: tunnel devices, split‐gate transistors/quantum point contacts, and other nanoscale systems. For any real‐world applications, such as in charge pumps for quantum metrology or specific quantum information processing systems, one needs a strategy to narrow the standard deviation of the device parameters. Of the attributes specific to manufacturability, reproducibility needs further improvement, simple simulations are available, and reliability and service life can be inferred from earlier cryogenic experiments. There are many examples of papers working on the new forms of carbon, fullerenes, nanotubes, and graphene, but these are still in the realms of one‐offs in terms of individual or few devices, or very small and primitive integrated circuits. The same applies to other quasi‐monolayer electron systems.

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