Flash memory
2,812 resources related to Flash memory
IEEE Organizations related to Flash memory
Back to TopConferences related to Flash memory
Back to Top2020 Joint Conference of the IEEE International Frequency Control Symposium and International Symposium on Applications of Ferroelectrics (IFCS-ISAF)
Ferroelectric materials and applications
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAM
This conference is a forum for researchers and designers to present and discuss various aspects of VLSI design, EDA, embedded systems, and enabling technologies. The program will consist of regular paper sessions, special sessions, embedded tutorials, panel discussions, design contest, industrial exhibits and tutorials. This is the premier conference/exhibition in this area in India, attracting designers, EDA professionals, and EDA tool users. The program committee for the conference has a significant representation from the EDA research community and a large fraction of the papers published in this conference are EDA-related
2018 Annual Reliability and Maintainability Symposium (RAMS)
Scope:Tutorials and original papers on reliability, maintainability, safety, risk management, and logistics
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
The DATE conference addresses all aspects of research into technologies for electronic and embedded system engineering. It covers the design process, test, and automation tools for electronics ranging from integrated circuits to distributed embedded systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecoms, wireless communications, multimedia, healthcare, smart energy and automotive systems. Companies also present innovative industrial designs to foster the feedback fromrealworld design to research. DATE also hosts a number of special sessions, events within the main technical programme such as panels, hot-topic sessions, tutorials and workshops technical programme such as panels, hot-topic sessions, tutorials and workshops.
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Periodicals related to Flash memory
Back to TopCircuits and Systems for Video Technology, IEEE Transactions on
Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...
Circuits and Systems II: Express Briefs, IEEE Transactions on
Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.
Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)
Communications, IEEE Transactions on
Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...
Components and Packaging Technologies, IEEE Transactions on
Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.
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Xplore Articles related to Flash memory
Back to TopScanrom, a novel non-volatile memory cell storing 9 bits
[{u'author_order': 1, u'affiliation': u'IMEC, Leuven, Belgium', u'full_name': u'M. Rosmeulen'}, {u'author_order': 2, u'affiliation': u'IMEC, Leuven, Belgium', u'full_name': u'J. Van Houdt'}, {u'author_order': 3, u'affiliation': u'IMEC, Leuven, Belgium', u'full_name': u'L. Haspeslagh'}, {u'author_order': 4, u'affiliation': u'IMEC, Leuven, Belgium', u'full_name': u'K. De Meyer'}] Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., None
We present a novel non-volatile memory cell based on a dual-gate transistor with an ONO charge-trapping dielectric underneath the drain-side gate. Multiple bits are stored along the width of the device. By contacting the gates from both sides and applying an appropriate bias difference to each, the individual bits are addressed for both reading and writing. We experimentally demonstrate reading ...
Vertical floating-gate 4.5F/sup 2/ split-gate NOR flash memory at 110nm node
[{u'author_order': 1, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'full_name': u'D. Lee'}, {u'author_order': 2, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'full_name': u'F. Tsui'}, {u'author_order': 3, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'full_name': u'Jeng-Wei Yang'}, {u'author_order': 4, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'full_name': u'Feng Gao'}, {u'author_order': 5, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'full_name': u'Wen-Juei Lu'}, {u'author_order': 6, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'full_name': u'Yeeheng Lee'}, {u'author_order': 7, u'affiliation': u'Silicon Storage Technol. Inc., Sunnyvale, CA, USA', u'full_name': u'Chi-Tsai Chen'}, {u'author_order': 8, u'full_name': u'V. Huang'}, {u'author_order': 9, u'full_name': u'Pin-Yao Wang'}, {u'author_order': 10, u'full_name': u'M. H. Liu'}, {u'author_order': 11, u'full_name': u'H. C. Hsu'}, {u'author_order': 12, u'full_name': u'S. Chang'}, {u'author_order': 13, u'full_name': u'S. Y. Chang'}, {u'author_order': 14, u'full_name': u'H. Van Tran'}, {u'author_order': 15, u'full_name': u'J. Frayer'}, {u'author_order': 16, u'full_name': u'Yaw-Wen Hu'}, {u'author_order': 17, u'full_name': u'B. Yeh'}, {u'author_order': 18, u'full_name': u'B. Chen'}] Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., None
We present the structural and electrical characteristics of the latest generation of a self-aligned split-gate NOR memory incorporating a vertical floating-gate channel having 4.5F/sup 2/ area on 110 nm half-pitch rules. With enhanced electric fields for erase and programming, the cell achieves erase time < 1 ms and program time < 10 /spl mu/s at 100nA programming current. These results ...
[{u'author_order': 1, u'affiliation': u'Dept. of Electr. & Comput. Eng., Lehigh Univ., Bethlehem, PA, USA', u'full_name': u'Y. Wang'}, {u'author_order': 2, u'affiliation': u'Dept. of Electr. & Comput. Eng., Lehigh Univ., Bethlehem, PA, USA', u'full_name': u'Y. Zhao'}, {u'author_order': 3, u'affiliation': u'Dept. of Electr. & Comput. Eng., Lehigh Univ., Bethlehem, PA, USA', u'full_name': u'B. M. Khan'}, {u'author_order': 4, u'affiliation': u'Dept. of Electr. & Comput. Eng., Lehigh Univ., Bethlehem, PA, USA', u'full_name': u'C. L. Doherty'}, {u'author_order': 5, u'affiliation': u'Dept. of Electr. & Comput. Eng., Lehigh Univ., Bethlehem, PA, USA', u'full_name': u'J. D. Krayer'}, {u'author_order': 6, u'affiliation': u'Dept. of Electr. & Comput. Eng., Lehigh Univ., Bethlehem, PA, USA', u'full_name': u'M. H. White'}] International Semiconductor Device Research Symposium, 2003, None
A novel SONOS (polysilicon-oxide-nitride-oxide-silicon) nonvolatile flash memory device which uses hot hole injection through the bottom oxide for write and tunneling to/from the gate through a thin top oxide for erase, with reduced power consumption, improved retention and subthreshold swing is proposed. The dynamic characteristics along with comparisons to NROM technology, forward/reverse read IDS ∼ IGS characteristics, programming speeds and ...
Overerase phenomena: an insight into flash memory reliability
[{u'author_order': 1, u'affiliation': u'Dipt. di Ingegneria, Univ. of Ferrara, Italy', u'full_name': u'A. Chimenton'}, {u'author_order': 2, u'affiliation': u'Dipt. di Ingegneria, Univ. of Ferrara, Italy', u'full_name': u'P. Pellati'}, {u'author_order': 3, u'affiliation': u'Dipt. di Ingegneria, Univ. of Ferrara, Italy', u'full_name': u'P. Olivo'}] Proceedings of the IEEE, 2003
The most important reliability issues related to the erasing operation in flash memories are, still today, caused by single bit failures. In particular, the overerase of tail and fast bits affects the threshold voltage distribution width, causing bit-line leakage that produces read/verify circuitry malfunctions, affects the programming efficiency due to voltage drop, and causes charge-pump circuitry failure. This brief overview ...
Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories
[{u'author_order': 1, u'affiliation': u'School of Electrical Engineering, Seoul National University, Shillim-dong, Kwanak-gu, Seoul 151-742 Korea. phone: 82-2-880-9372; fax: 82-2-874-7271', u'full_name': u'Wei Liu'}, {u'author_order': 2, u'affiliation': u'School of Electrical Engineering, Seoul National University, Shillim-dong, Kwanak-gu, Seoul 151-742 Korea. phone: 82-2-880-9372; fax: 82-2-874-7271', u'full_name': u'Junrye Rho'}, {u'author_order': 3, u'affiliation': u'School of Electrical Engineering, Seoul National University, Shillim-dong, Kwanak-gu, Seoul 151-742 Korea. phone: 82-2-880-9372; fax: 82-2-874-7271; e-mail: wysung@snu.ac.kr', u'full_name': u'Wonyong Sung'}] 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, None
As the reliability is a critical issue for new generation multi-level cell (MLC) flash memories, there is growing call for fast and compact error correction code (ECC) circuit with minimum impact on memory access time and chip area. This paper presents a high-throughput and low-power ECC scheme for MLC NAND flash memories. The BCH encoder and decoder architecture features byte-wise ...
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Educational Resources on Flash memory
Back to TopIEEE.tv Videos
What's New in Storage Devices - Jim Gathman from IBM 
The Memory of Cars Talk by Tom Coughlin 
ISSCC 2012 - Eli Harari Plenary 
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017 
Improved Deep Neural Network Hardware Accelerators Based on Non-Volatile-Memory: the Local Gains Technique: IEEE Rebooting Computing 2017 
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation 
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing 
Analog to Digital Types 
Impact of Linearity and Write Noise of Analog Resistive Memory: IEEE Rebooting Computing 2017 
High-Bandwidth Memory Interface Design 
HKN: The Next Big Thing Panel 
Array storing and retrieval 
Robotics History: Narratives and Networks Oral Histories: Barbara Hayes Roth 
Rajiv V. Joshi - 2018 Daniel E. Noble Award for Emerging Technologies at IEEE ISSCC 
Neural Cognitive Robot: Learning, Memory and Intelligence 
Jaynie Shorb from Broadcom at WIE ILC 2016 
IEEE Medal of Honor Recipient (2009): Dr. Robert Dennard 
Accelerating Machine Learning with Non-Volatile Memory: Exploring device and circuit tradeoffs - Pritish Narayanan: 2016 International Conference on Rebooting Computing 
IEEE Expert Now 
Rebooting Computing Panel - Stan Williams: 2016 Technology Time Machine IEEE-USA E-Books
The most important requirement for NAND flash memory is a low bit cost. This chapter discusses the NAND flash memory cell and its scaling technologies. Requirements for isolation in NAND flash memory cell are more severe than other devices due to high-voltage operation during programming. Therefore, it was difficult to scale down of local oxidation of silicon (LOCOS) isolation width beyond 1.5-?>m width due to boron diffusion from isolation bottom by LOCOS oxidation process. Then, a new field through implantation (FTI) process was developed. Next, the self-aligned shallow trench isolation cell (SA-STI cell) with floating gate (FG) wing had been developed. The chapter presents the planar FG cell and also discusses the side wall transfer-transistor (SWATT) cell as alternate memory cell technology for a multilevel NAND flash memory cell. Finally, it presents other advanced NAND flash device technologies.
Principle of Nand Flash Memory
This chapter shows the single-cell architecture of NAND flash memory. One NAND string consists of 32 series-connected stacked gate memory transistors and two select gate transistors. The scaling of a high-voltage transistor (HV Tr) is one of the important challenges for NAND flash memories. Several program and erase schemes were considered to use a NAND flash memory product in early stage of development. There are several program boosting schemes for multilevel NAND flash cells. The first one is a conventional selfboosting (SB) scheme. The second one is a local self-boosting scheme. The third one is the erase-area self-boosting scheme (EASB). EASB was widely used for multilevel cell (MLC) to obtain a higher boosting voltage. In order to relax high electric field, the self-boosting scheme is becoming a more advanced and complicated scheme for each generation of NAND flash memory.
Challenges Of Three-Dimensional Nand Flash Memory
This chapter introduces several types of three-dimensional (3D) NAND flash memory cells. It first addresses the challenges of 3D NAND flash memory and discusses data retention issues. The data retention characteristic of SONOS cell has problems of quick charge loss and large Vt shift in retention bake because of charge detrapping through thinner tunnel oxide. The chapter presents the analysis results of program disturb in 3D NAND cells. The program disturb mechanisms of 3D NAND cells are much different from that of 2D NAND cells, because cell structure and array architecture are totally changed. The cell current is much decreased in the 3D NAND cell, because channel material is changed from crystal Si (substrate Si) to poly-Si. The chapter describes the new structure of the peripheral circuit under cell array. Finally, it discusses the future trend of the 3D NAND cell.
Scaling Challenge Of Nand Flash Memory Cells
This chapter discusses the scaling challenges of the NAND flash memory cell with a multilevel cell beyond 20-nm feature sizes. One important physical phenomenon is the floating-gate (FG) capacitive coupling interference that causes a Vt shift by programming neighbor cells. An increase in Vt distribution width will result in the degradation of read window margin (RWM). The other major physical phenomena to have an impact on RWM are electron injection spread (EIS) and random telegraph noise (RTN). Except for the RWM degradation, there are several other problems, such as control gate (CG) formations between FGs, the word line (WL) high-field problem, and reducing the number of stored electrons. The RWM of a self-aligned shallow trench isolation cell (SA-STI cell) is discussed for NAND flash memories over 2X to 0X-nm generations. The chapter also discusses several scaling problems and limitations over 2X to 0X-nm generations.
Reliability Of Nand Flash Memory
Reliability of NAND flash memory is more interesting than that of other semiconductor devices. Program and erase of NAND flash perform by electron injection and emission to/from floating gate (FG). There are several methods of electron injection and emission. For electron injection, there are two methods, namely channel hot electron (CHE) injection and Fowler-Nordheim tunneling (FN-t) injection. Data retention is degraded by electron and hole traps in tunnel oxide. Detrapping of trapped charges in tunnel oxide is a major root cause of Vt shift during the data retention test. Read disturb failure is mainly caused in the erase state after program/erase cycling stress. The stress-induced leakage current (SILC), which is generated by program/erase cycling stress, is major root cause for the read-disturb phenomena. The mechanism of erratic over program is considered to be an excess electron injection at hole trap sites in tunnel oxide.
Prospects and Challenges of NextGeneration Flash Memory Devices
This chapter contains sections titled: * Introduction * Scaling challenges * Technological innovations * Conclusions