Conferences related to Emulation

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2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.


2013 International Symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS)

This is a forum for professionals involved in performance evaluation of computer and telecommunication systems. Performance evaluation of computer systems and networks has progressed rapidly in the past decade and has begun to approach maturity. Significant progress has been made in analytic modeling, simulation, and measurement approaches for performance evaluation of computer and telecommunication systems.

  • 2012 International Symposium on Performance Evaluation of Computer & Telecommunication Systems (SPECTS)

    This annual international conference is a forum for professional research people involved in performance evaluation of computer and telecommunication/networking systems, including analytic modeling, simulation, and measurement. Moreover, main topics include tools, methodologies, applications advances in the performance evaluation field.

  • 2011 International Symposium on Performance Evaluation of Computer & Telecommunication Systems (SPECTS)

    This is a forum for professionals involved in performance evaluation of computer and telecommunication systems. Performance evaluation of computer systems and networks has progressed rapidly and is close to maturity. Significant progress has been made in analytic modeling, simulation, and measurement approaches for performance evaluation of computer and telecommunication systems.

  • 2010 International Symposium on Performance Evaluation of Computer & Telecommunication Systems (SPECTS)

    This is a forum for professionals involved in performance evaluation of computer and telecommunication systems. Performance evaluation of computer systems and networks has progressed rapidly and is close to maturity. Significant progress has been made in analytic modeling, simulation, and measurement approaches for performance evaluation of computer and telecommunication systems.


2012 22nd International Conference on Field Programmable Logic and Applications (FPL)

Applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration of field programmable logic.

  • 2011 International Conference on Field Programmable Logic and Applications (FPL)

    FPL is the first and largest conference covering the rapidly growing area of field-programmable logic. Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion on FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration.

  • 2010 International Conference on Field Programmable Logic and Applications (FPL)

    The conference objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs and other field-programmable devices, their architectures and design methods, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2009 International Conference on Field Programmable Logic and Applications (FPL)

    The conference objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs and other field-programmable devices, their architectures and design methods, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2008 International Conference on Field Programmable Logic and Applications (FPL)

    Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2007 International Conference on Field Programmable Logic and Applications (FPL)

    Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2006 International Conference on Field Programmable Logic and Applications (FPL)


2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation (PADS)

The PADS workshop is the premiere conference on parallel and distributed simulation methods and applications and is soliciting papers in all aspects of simulation technology.

  • 2010 IEEE 24th Workshop on Principles of Advanced and Distributed Simulation (PADS)

    The Workshop on Principles of Advanced and Distributed Simulation (PADS), formerly called Parallel and Distributed Simulation, is soliciting papers in all aspects of simulation technology, expanding the traditional focus on parallel and distributed simulation methods and applications.

  • 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation (PADS)

    Techniques include those pertaining to parallel and distributed simulation, distributed interactive simulation, distributed virtual environments and modeling methodology. Applications of these these techniques to large scale engineering, scientific or economis simulations are of great interest.

  • 2008 ACM/IEEE/SCS Workshop on Principles of Advanced and Distributed Simulation (PADS)

    The PADS workshop is soliciting papers in all aspects of simulation technology, expanding the traditional focus on parallel and distributed simulation methods and applications. Specifically, the steering and program committees look forward to high-quality paper submissions in the following areas: * The construction of simulation engines using advanced computer science technology. * Techniques for constructing scalable simulations. * Advanced modeling techniques that allow solution of previous


2012 IEEE 18th International Conference on Parallel and Distributed Systems (ICPADS)

The conference provides an international forum for scientists, engineers and users to exchange and share their experiences, new ideas, and latest research results on all aspects of parallel and distributed systems. Contributions are solicited in all areas of parallel and distributed systems research and applications.


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Periodicals related to Emulation

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Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Parallel and Distributed Systems, IEEE Transactions on

IEEE Transactions on Parallel and Distributed Systems (TPDS) is published monthly. Topic areas include, but are not limited to the following: a) architectures: design, analysis, and implementation of multiple-processor systems (including multi-processors, multicomputers, and networks); impact of VLSI on system design; interprocessor communications; b) software: parallel languages and compilers; scheduling and task partitioning; databases, operating systems, and programming environments for ...


Software Engineering, IEEE Transactions on

Specification, development, management, test, maintenance, and documentation of computer software.


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Xplore Articles related to Emulation

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Position-dependent control of numerical integration in circuit simulation

K. Strunz IEEE Transactions on Circuits and Systems II: Express Briefs, 2004

In circuit simulators based on nodal analysis techniques, one numerical integration method is typically used to solve all differential equations. The properties of this method determine to a large extent the types of waveforms which can be simulated accurately. In this work, a concept for the position dependent control of numerical integration to simulate waveforms with very diverse characteristics is ...


A partial-correctness semantics for modelling assembler programs

G. Watson; C. Fidge First International Conference onSoftware Engineering and Formal Methods, 2003.Proceedings., 2003

Previous work on formally modelling and analysing program compilation has shown the need for a simple and expressive semantics for assembler level programs. Assembler programs contain unstructured jumps and previous formalisms have modelled these by using continuations, or by embedding the program in an explicit emulator. We propose a simpler approach, which uses techniques from compiler theory in a formal ...


Testing microprocessor-based boards (VXI/PXI Plug and Play technology applications)

L. Gutterman Proceedings AUTOTESTCON 2003. IEEE Systems Readiness Technology Conference., 2003

Testing microprocessor-based boards (μP) could be a challenge even for the experienced test engineer. This paper reviews the related challenges and available test philosophies for the functional testing of these products.


Towards Cycle-Accurate Emulation of Cortex-M Code to Detect Timing Side Channels

Johannes Bauer; Felix Freiling 2016 11th International Conference on Availability, Reliability and Security (ARES), 2016

Leakage of information through timing side channels is a problem for all sorts of computing machinery, but the impact of such channels is especially dramatic on embedded systems. The reason for this is that these environments allow attackers to exploit small timing differences down to clock cycle accuracy. On the defensive side it is therefore advisable to evaluate cautiously if ...


Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Ernesto Sanchez; Luca Sterpone; Anees Ullah 2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014

Hardware fault emulation for Application Specific Integrated Circuits (ASICs) on FPGAs can considerably reduce the time required for the fault simulation. This paper presents a methodology to emulate ASIC faults on state-of-the-art FPGAs. The fault emulation is achieved by following a fully automated process consisting of: constrained technology mapping of ASIC net-list; creation of fault dictionary, generation of faulty partial ...


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Educational Resources on Emulation

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eLearning

Position-dependent control of numerical integration in circuit simulation

K. Strunz IEEE Transactions on Circuits and Systems II: Express Briefs, 2004

In circuit simulators based on nodal analysis techniques, one numerical integration method is typically used to solve all differential equations. The properties of this method determine to a large extent the types of waveforms which can be simulated accurately. In this work, a concept for the position dependent control of numerical integration to simulate waveforms with very diverse characteristics is ...


A partial-correctness semantics for modelling assembler programs

G. Watson; C. Fidge First International Conference onSoftware Engineering and Formal Methods, 2003.Proceedings., 2003

Previous work on formally modelling and analysing program compilation has shown the need for a simple and expressive semantics for assembler level programs. Assembler programs contain unstructured jumps and previous formalisms have modelled these by using continuations, or by embedding the program in an explicit emulator. We propose a simpler approach, which uses techniques from compiler theory in a formal ...


Testing microprocessor-based boards (VXI/PXI Plug and Play technology applications)

L. Gutterman Proceedings AUTOTESTCON 2003. IEEE Systems Readiness Technology Conference., 2003

Testing microprocessor-based boards (μP) could be a challenge even for the experienced test engineer. This paper reviews the related challenges and available test philosophies for the functional testing of these products.


Towards Cycle-Accurate Emulation of Cortex-M Code to Detect Timing Side Channels

Johannes Bauer; Felix Freiling 2016 11th International Conference on Availability, Reliability and Security (ARES), 2016

Leakage of information through timing side channels is a problem for all sorts of computing machinery, but the impact of such channels is especially dramatic on embedded systems. The reason for this is that these environments allow attackers to exploit small timing differences down to clock cycle accuracy. On the defensive side it is therefore advisable to evaluate cautiously if ...


Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Ernesto Sanchez; Luca Sterpone; Anees Ullah 2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014

Hardware fault emulation for Application Specific Integrated Circuits (ASICs) on FPGAs can considerably reduce the time required for the fault simulation. This paper presents a methodology to emulate ASIC faults on state-of-the-art FPGAs. The fault emulation is achieved by following a fully automated process consisting of: constrained technology mapping of ASIC net-list; creation of fault dictionary, generation of faulty partial ...


More eLearning Resources

IEEE-USA E-Books

  • Whole Brain Emulation

    This chapter contains sections titled: 2.1 Copying the Brain, 2.2 Three Stages of Whole Brain Emulation, 2.3 The Technology of Brain Mapping, 2.4 The Technology of Neural Simulation, 2.5 Brain-Scale Computation, 2.6 Robotics: The Technology of Embodiment, 2.7 Virtual Embodiment, 2.8 Emulation and Enhancement

  • Three Sources of Information in Social Learning

    This chapter contains sections titled: Three Sources of Information in Social Learning, Emulation and Imitation, A New, Multidimensional Framework, Conclusion, Acknowledgments, Note, References

  • The EPON PHY

    This chapter contains sections titled: Introduction Overview of the chapter What to expect and who would benefit from reading this chapter 65: The reader's digest The Gigabit Ethernet layers Point-to-point emulation Burst mode operation Forward error correction (FEC) for 1000BASE-PX Delay through the PHY Summary of concepts covered in this chapter Additional references

  • Emulation

    This chapter contains sections titled: Notes, Works Cited

  • Design of a Multicomputer Dataparallel C Compiler

    This chapter contains sections titled: Target Software Environment, The Routing Library, Processor Synchronization, Virtual Processor Emulation, Implementing Global Name Space, Compiling Member Functions, Translation of a Simple Program, Summary

  • Social Adjustment in Britain, 1867–1914

    This chapter contains sections titled: Intimations of Mortality, The Civic Universities, The Need for Central Stimulus, The Rise of New Industrial States: Japan, The Training of Engineers, The Growing Concern of the Government, The Spirit of Emulation Fostered, The Bell Tolls Again, 1887, The Iron and Steel Institute, 1869, The Mining Associations, 1887-1889, Association for the Promotion of Technical Education, 1887, The Fabians, Collateral Developments, An Early Operationalist, The Service Groups of Municipal Socialism, The New Professionals, The British Standards Institution, The Critics Within, Government Patronage of Engineering, 1900-1914, An Engineering Pressure Group

  • End-to-End Communications System Model with Focus on Payload

    This chapter contains sections titled: Introduction Considerations for Both Software Simulation and Hardware Emulation Additional Considerations for Simulation Additional Considerations for Emulation References

  • Finding the Material in the Virtual: The Case of Emulation

    In 2003, Pittburgh's Andy Warhol Museum revealed a series of artworks by Warhol that had been lost for many years (Heddaya 2014). In collaboration with artist Cory Arcangel and computer scientists from Carnegie Mellon University, the museum had recovered a number of digital images that Warhol had created on an early Commodore Amiga personal computer.

  • Co-Emulation: The Case for a Global Hypernetwork Society

    This chapter contains sections titled: From Networks Today to Hypernetworks Tomorrow, Informatization in Historical Perspective, Informatization as an Economic Transition, Informatization as a Sociological Transition, Informatization as a Civilizational Transition, How the Hypernetwork Society Will Be Shaped, Co-Emulation in the Global Hypernetwork Society

  • Internetworking Framework Architectures in IP and ATM

    Introduction LAN Emulation over ATM (LANE) IP Switching Multiprotocol over ATM (MPOA) MPOA Functional Overview and Data Transfer Procedures Flow Characterization and Connection Management in MPOA Multiprotocol Label Switching (MPLS) MPLS Architecture and Functions The Label Distribution Protocol (LDP) Explicit and Constrained Routed LDP (CR-LDP) The Generic MPLS Encapsulation Structure



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