Dynamic voltage scaling
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)
technology, architecture, circuits, tools, systems, software and applications
A-SSCC 2012 is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Fundamental technologies used in the control and conversion of electric power. Topics include dc-to- dc converter design, direct off-line switching power supplies, inverters, controlled rectifiers, control techniques, modeling, analysis and simulation techniques, the application of power circuit components (power semiconductors, magnetics, capacitors), and thermal performance of electronic power systems.
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...
Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.
Thiele, L.; Chakraborty, S.; Maxiaguine, A. Hardware/Software Codesign and System Synthesis, 2005. CODES+ISSS '05. Third IEEE/ACM/IFIP International Conference on, 2005
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our scheme over previously published DVS schemes is its ability to provide hard QoS guarantees while still achieving considerable energy savings. Our scheme can handle workloads characterized by both, the data-dependent variability in the ...
Kutter, C. Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on, 2006
Summary form only given. System on chips (SoC) for mobile devices, such as GSM/EDGE/UMTS, have strongly conflicting requirements. On one hand the demand for processing performance is steadily increasing with every new standard and on the other hand extremely low power dissipation is demanded. The performance demands vary strongly, depending on the phone modes and activities e.g. stand- by mode ...
Huang, S.; Chunhong Chen; Ahmadi, M.; Mokrian, P. Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, 2002
With the development of mobile and portable devices, there is a strong need for reducing the energy in integrated circuit chips. Dynamic voltage scaling (DVS) techniques reduce energy consumption by changing the operating speed and voltage in real-time, based on the workload of the operation. In this paper, we address the optimal variable voltage scheduling problem for different workloads to ...
Abdelhak, S.; Gurram, C.S.; Ghosh, S.; Bayoumi, M. Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on, 2010
Extending the wireless sensor network's lifetime has been the aim of several research efforts. Distributed in-network processing arises as a viable solution to extend the network's lifetime. It avoids assigning heavy computations to a single node which might otherwise lead to its significant energy depletion. Task scheduling and allocation play a major role in the efficiency of the distribution. This ...
Chandrasena, L.H.; Liebelt, M.J. Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, 2000
In this paper we propose a workload distribution based quantized voltage level selection method called Data Dependent Level Selection (DDLS) for minimizing energy in dynamic supply voltage scaling systems. In previous works, the voltage levels have been selected by dividing the maximum normalized workload by the number of quantized voltage levels. The existing techniques place no emphasis on workload characteristics ...
Ellis, Wayne Effects of Reliability Mechanisms On VLSI Circuit Functionality, 2004
This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to ...
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