Dynamic voltage scaling

View this topic in
Dynamic voltage scaling is a power management technique in computer architecture, where the voltage used in a component is increased or decreased, depending upon circumstances. (Wikipedia.org)






Conferences related to Dynamic voltage scaling

Back to Top

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)


2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)

technology, architecture, circuits, tools, systems, software and applications


2012 IEEE Asian Solid-State Circuits Conference (A-SSCC)

A-SSCC 2012 is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields.

  • 2011 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    A-SSCC is becoming one of the foremost global forums for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers opportunities for technical papers and educational events related to integrated circuits: analog, data converters, digital, SoC, RF, wireline & mixed-signal circuits, emerging technologies and applications and memory.

  • 2010 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    A-SSCC is becoming one of the foremost global forums for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers opportunities for technical papers and educational events related to integrated circuits: analog, data converters, digital, SoC, RF, wireline & mixed-signal circuits, emerging technologies and applications and memory.

  • 2009 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    The IEEE A-SSCC 2009 (Asian Solid-State Circuits Conference) is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields.

  • 2008 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    The IEEE A-SSCC 2008 (Asian Solid-State Circuits Conference) is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields. The conference is supported by the IEEE Solid-State Circuits Society and will be held in Asia.



Periodicals related to Dynamic voltage scaling

Back to Top

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Power Electronics, IEEE Transactions on

Fundamental technologies used in the control and conversion of electric power. Topics include dc-to- dc converter design, direct off-line switching power supplies, inverters, controlled rectifiers, control techniques, modeling, analysis and simulation techniques, the application of power circuit components (power semiconductors, magnetics, capacitors), and thermal performance of electronic power systems.


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.



Most published Xplore authors for Dynamic voltage scaling

Back to Top

Xplore Articles related to Dynamic voltage scaling

Back to Top

ParaScale: exploiting parametric timing analysis for real-time schedulers and dynamic voltage scaling

S. Mohan; F. Mueller; W. Hawkins; M. Root; C. Healy; D. Whalley 26th IEEE International Real-Time Systems Symposium (RTSS'05), 2005

Static timing analysis safely bounds worst-case execution times to determine if tasks can meet their deadlines in hard real-time systems. However, conventional timing analysis requires that the upper bound of loops be known statically, which limits its applicability. Parametric timing analysis methods remove this constraint by providing the WCET as a formula parameterized on loop bounds. This paper contributes a ...


Optimal dynamic voltage scaling in power-limited systems with real-time constraints

Jianfeng Mao; Qianchuan Zhao; C. G. Cassandras Decision and Control, 2004. CDC. 43rd IEEE Conference on, 2004

Dynamic voltage scaling is used in power-limited systems such as sensor networks as a means of conserving energy and prolonging their life. We consider a setting in which the tasks performed by such a system are nonpreemptive, aperiodic and have uncertain arrival times. Our objective is to control the processing rate over different tasks so as to minimize energy subject ...


Frame-based dynamic voltage and frequency scaling for a MPEG decoder

Kihwan Choi; K. Dantu; Wei-Chung Cheng; M. Pedram Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002

This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption while maintaining a quality of service (QoS) constraint. The computational workload for an incoming frame is predicted using a frame-based history so that the processor voltage and frequency can be scaled to provide: the exact amount of computing power needed to ...


A holistic approach to designing energy-efficient cluster interconnects

E. J. Kim; G. M. Link; K. H. Yum; N. Vijaykrishnan; M. Kandemir; M. J. Irwin; C. R. Das IEEE Transactions on Computers, 2005

Designing energy-efficient clusters has recently become an important concern to make these systems economically attractive for many applications. Since the cluster interconnect is a major part of the system, the focus of this paper is to characterize and optimize the energy consumption in the entire interconnect. Using a cycle-accurate simulator of an InfiniBand Architecture (IBA) compliant interconnect fabric and actual ...


The compatibility analysis of thread migration and DVFS in multi-core processor

Dongkeun Oh; Charlie Chung Ping Chen; NamSung Kim; Yu Hen Hu Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010

Integrating multiple cores into a processor increases the heat density significantly, which often constrains the maximum performance of such a processor. There have been many techniques using dynamic voltage and frequency scaling (DVFS) and thread migration to manipulate heat dissipation in thermally-constrained multi-core processors. However, most of them were analyzed and applied individually for optimizing the performance of the multi- ...


More Xplore Articles

Educational Resources on Dynamic voltage scaling

Back to Top

eLearning

ParaScale: exploiting parametric timing analysis for real-time schedulers and dynamic voltage scaling

S. Mohan; F. Mueller; W. Hawkins; M. Root; C. Healy; D. Whalley 26th IEEE International Real-Time Systems Symposium (RTSS'05), 2005

Static timing analysis safely bounds worst-case execution times to determine if tasks can meet their deadlines in hard real-time systems. However, conventional timing analysis requires that the upper bound of loops be known statically, which limits its applicability. Parametric timing analysis methods remove this constraint by providing the WCET as a formula parameterized on loop bounds. This paper contributes a ...


Optimal dynamic voltage scaling in power-limited systems with real-time constraints

Jianfeng Mao; Qianchuan Zhao; C. G. Cassandras Decision and Control, 2004. CDC. 43rd IEEE Conference on, 2004

Dynamic voltage scaling is used in power-limited systems such as sensor networks as a means of conserving energy and prolonging their life. We consider a setting in which the tasks performed by such a system are nonpreemptive, aperiodic and have uncertain arrival times. Our objective is to control the processing rate over different tasks so as to minimize energy subject ...


Frame-based dynamic voltage and frequency scaling for a MPEG decoder

Kihwan Choi; K. Dantu; Wei-Chung Cheng; M. Pedram Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002

This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption while maintaining a quality of service (QoS) constraint. The computational workload for an incoming frame is predicted using a frame-based history so that the processor voltage and frequency can be scaled to provide: the exact amount of computing power needed to ...


A holistic approach to designing energy-efficient cluster interconnects

E. J. Kim; G. M. Link; K. H. Yum; N. Vijaykrishnan; M. Kandemir; M. J. Irwin; C. R. Das IEEE Transactions on Computers, 2005

Designing energy-efficient clusters has recently become an important concern to make these systems economically attractive for many applications. Since the cluster interconnect is a major part of the system, the focus of this paper is to characterize and optimize the energy consumption in the entire interconnect. Using a cycle-accurate simulator of an InfiniBand Architecture (IBA) compliant interconnect fabric and actual ...


The compatibility analysis of thread migration and DVFS in multi-core processor

Dongkeun Oh; Charlie Chung Ping Chen; NamSung Kim; Yu Hen Hu Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010

Integrating multiple cores into a processor increases the heat density significantly, which often constrains the maximum performance of such a processor. There have been many techniques using dynamic voltage and frequency scaling (DVFS) and thread migration to manipulate heat dissipation in thermally-constrained multi-core processors. However, most of them were analyzed and applied individually for optimizing the performance of the multi- ...


More eLearning Resources

IEEE.tv Videos

No IEEE.tv Videos are currently tagged "Dynamic voltage scaling"

IEEE-USA E-Books

No IEEE-USA E-Books are currently tagged "Dynamic voltage scaling"



Standards related to Dynamic voltage scaling

Back to Top

No standards are currently tagged "Dynamic voltage scaling"


Jobs related to Dynamic voltage scaling

Back to Top