Dynamic voltage scaling

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Dynamic voltage scaling is a power management technique in computer architecture, where the voltage used in a component is increased or decreased, depending upon circumstances. (Wikipedia.org)






Conferences related to Dynamic voltage scaling

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2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)


2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)

technology, architecture, circuits, tools, systems, software and applications


2012 IEEE Asian Solid-State Circuits Conference (A-SSCC)

A-SSCC 2012 is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields.

  • 2011 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    A-SSCC is becoming one of the foremost global forums for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers opportunities for technical papers and educational events related to integrated circuits: analog, data converters, digital, SoC, RF, wireline & mixed-signal circuits, emerging technologies and applications and memory.

  • 2010 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    A-SSCC is becoming one of the foremost global forums for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers opportunities for technical papers and educational events related to integrated circuits: analog, data converters, digital, SoC, RF, wireline & mixed-signal circuits, emerging technologies and applications and memory.

  • 2009 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    The IEEE A-SSCC 2009 (Asian Solid-State Circuits Conference) is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields.

  • 2008 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    The IEEE A-SSCC 2008 (Asian Solid-State Circuits Conference) is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields. The conference is supported by the IEEE Solid-State Circuits Society and will be held in Asia.



Periodicals related to Dynamic voltage scaling

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Power Electronics, IEEE Transactions on

Fundamental technologies used in the control and conversion of electric power. Topics include dc-to- dc converter design, direct off-line switching power supplies, inverters, controlled rectifiers, control techniques, modeling, analysis and simulation techniques, the application of power circuit components (power semiconductors, magnetics, capacitors), and thermal performance of electronic power systems.


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.




Xplore Articles related to Dynamic voltage scaling

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A Novel Voltage Stabilization Control Scheme for Stand-alone Wind Energy Conversion Systems

Sharaf, A.M.; Aljankawey, A.; Altas, I.H. Clean Electrical Power, 2007. ICCEP '07. International Conference on, 2007

This paper proposes a novel low cost FACTS based voltage stabilization scheme for a stand-alone wind energy conversion systems using self excited squirrel- cage induction generator (SEIG) driven by a wind turbine and interfaced to electric load. The new control scheme is designed not only to ensure bus voltage stabilization, but also to improve energy utilization using a low-cost PWM-switched ...


A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications

Wang, Y.; Ahn, H.; Bhattacharya, U.; Coan, T.; Hamzaoglu, F.; Hafez, W.; Jan, C.-H.; Kolar, P.; Kulkarni, S.; Lin, J.; Ng, Y.; Post, I.; Wei, L.; Zhang, Y.; Zhang, K.; Bohr, M. Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, 2007

A low-power high-speed SRAM macro is implemented in an ultra-low-power 8M 65nm CMOS for mobile applications. The 1Mb macro features a 0.667μm2 low-leakage memory cell and operates with supply voltage from 0.5V to 1.2V. It operates at a frequency of 1.1 GHz at 1.2V and 250MHz at 0.7V. Leakage is reduced to 12μA/Mb at the data retention voltage of 0.5V. ...


A Partition-Based Voltage Scaling Algorithm Using Dual Supply Voltages for Low Power Designs

Hung Hsie Lee; Sung Han Tsai; Jun-Cheng Chi; Mely Chen Chi VLSI Design, Automation and Test, 2006 International Symposium on, 2006

We proposed an effective voltage scaling technique to assign the supply voltage to gates in the circuit of dual power supplies. The algorithm is composed of a greedy voltage assignment phase and an iterative voltage re- assignment refinement phase. It reduces the total power without performance degradation. We apply the algorithm to several test cases. It shows that on average ...


Low Power 2:1 MUX for Barrel Shifter

Khandekar, P.D.; Subbaraman, S. Emerging Trends in Engineering and Technology, 2008. ICETET '08. First International Conference on, 2008

Adiabatic switching techniques based on energy recovery principle are one of the innovative solutions at circuit and logic level to achieve reduction in power. Many researchers had taken adder as a benchmark circuit but advantage of adiabatic can be taken only for a large digital circuit. Barrel shifter is an important block in the processor design and not much effort ...


High performance SOI DTMOS using a retrograde base with a low impurity surface channel

Feixia Yu; Cheng, M.-C.; Jun Xu Semiconductor Device Research Symposium, 2001 International, 2001

This paper presents a simulation-based investigation on 0.13 μm SOI dynamic threshold MOS (DTMOS) structures with uniform and retrograde base profiles. The base of the retrograde SOI DTMOS is split into a low impurity surface channel and a heavily doped body. The low impurity channel is able to provide high channel mobility, and the heavily doped body enhances the body ...


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Educational Resources on Dynamic voltage scaling

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eLearning

Effects of Reliability Mechanisms On VLSI Circuit Functionality

Ellis, Wayne Effects of Reliability Mechanisms On VLSI Circuit Functionality, 2004

This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to ...


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