Dynamic voltage scaling

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Dynamic voltage scaling is a power management technique in computer architecture, where the voltage used in a component is increased or decreased, depending upon circumstances. (Wikipedia.org)






Conferences related to Dynamic voltage scaling

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2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)


2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)

technology, architecture, circuits, tools, systems, software and applications


2012 IEEE Asian Solid-State Circuits Conference (A-SSCC)

A-SSCC 2012 is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields.

  • 2011 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    A-SSCC is becoming one of the foremost global forums for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers opportunities for technical papers and educational events related to integrated circuits: analog, data converters, digital, SoC, RF, wireline & mixed-signal circuits, emerging technologies and applications and memory.

  • 2010 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    A-SSCC is becoming one of the foremost global forums for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers opportunities for technical papers and educational events related to integrated circuits: analog, data converters, digital, SoC, RF, wireline & mixed-signal circuits, emerging technologies and applications and memory.

  • 2009 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    The IEEE A-SSCC 2009 (Asian Solid-State Circuits Conference) is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields.

  • 2008 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    The IEEE A-SSCC 2008 (Asian Solid-State Circuits Conference) is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields. The conference is supported by the IEEE Solid-State Circuits Society and will be held in Asia.



Periodicals related to Dynamic voltage scaling

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Power Electronics, IEEE Transactions on

Fundamental technologies used in the control and conversion of electric power. Topics include dc-to- dc converter design, direct off-line switching power supplies, inverters, controlled rectifiers, control techniques, modeling, analysis and simulation techniques, the application of power circuit components (power semiconductors, magnetics, capacitors), and thermal performance of electronic power systems.


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.



Most published Xplore authors for Dynamic voltage scaling

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Xplore Articles related to Dynamic voltage scaling

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Power-composition profile driven co-synthesis with power management selection for dynamic and leakage energy reduction

D. Wu; B. M. Al-Hashimi; M. T. Schmitz; P. Eles 8th Euromicro Conference on Digital System Design (DSD'05), 2005

Recent research has shown that the combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) yields high energy reductions in embedded systems. Nevertheless, the implementation of DVS and ABB requires a significant system cost, making it less attractive for many small systems. In this paper we demonstrate that it is possible to reduce this system cost and to ...


GPSDVS: An improved task-based dynamic voltage scaling scheme for general-purpose systems

Sookyoung Kim; T. L. Martin Proceedings 2005 IEEE International SOC Conference, 2005

We propose an improved task-based dynamic voltage scaling (DVS) scheme for general-purpose (GP) systems. It achieves more energy savings than existing task-based schemes at comparable performance preservation levels by automatically inferring the correct performance requirement type of each task, applying a suitable speed scaling strategy to it, and scaling CPU speed considering the impact of non real-time task schedulers and ...


Buffer Constrained Proactive Dynamic Voltage Scaling for Video Decoding Systems

Emrah Akyol; Mihaela van der Schaar 2007 IEEE International Conference on Image Processing, 2007

Significant power savings can be achieved on voltage/frequency configurable platforms by dynamically adapting the frequency and voltage according to the workload (complexity). Video decoding is one of the most complex tasks performed on such systems due to its computationally demanding operations like inverse filtering, interpolation, motion compensation and entropy decoding. Dynamically adapting the frequency and voltage for video decoding is ...


DVS for on-chip bus designs based on timing error correction

H. Kaul; D. Sylvester; D. Blaauw; T. Mudge; T. Austin Design, Automation and Test in Europe, 2005

On-chip buses are typically designed to meet performance constraints for worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern. This can result in significant performance slack at more typical operating conditions. We propose a dynamic voltage scaling (DVS) technique for buses, based on a double sampling latch which can detect and correct for delay errors without the ...


Temperature-Aware Scheduling: When is System-Throttling Good Enough?

Deepak Rajan; Philip S. Yu Web-Age Information Management, 2008. WAIM '08. The Ninth International Conference on, 2008

In computing centers, power-aware operating systems ensure that processor temperatures do not exceed a threshold by utilizing system-throttling. In this technique, the system load (or alternatively, the clock speed) is scaled when the temperature hits this threshold. At other times, the system operates at maximum load. In this paper, we show that such simple system-throttling rules are in fact the ...


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Educational Resources on Dynamic voltage scaling

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eLearning

Power-composition profile driven co-synthesis with power management selection for dynamic and leakage energy reduction

D. Wu; B. M. Al-Hashimi; M. T. Schmitz; P. Eles 8th Euromicro Conference on Digital System Design (DSD'05), 2005

Recent research has shown that the combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) yields high energy reductions in embedded systems. Nevertheless, the implementation of DVS and ABB requires a significant system cost, making it less attractive for many small systems. In this paper we demonstrate that it is possible to reduce this system cost and to ...


GPSDVS: An improved task-based dynamic voltage scaling scheme for general-purpose systems

Sookyoung Kim; T. L. Martin Proceedings 2005 IEEE International SOC Conference, 2005

We propose an improved task-based dynamic voltage scaling (DVS) scheme for general-purpose (GP) systems. It achieves more energy savings than existing task-based schemes at comparable performance preservation levels by automatically inferring the correct performance requirement type of each task, applying a suitable speed scaling strategy to it, and scaling CPU speed considering the impact of non real-time task schedulers and ...


Buffer Constrained Proactive Dynamic Voltage Scaling for Video Decoding Systems

Emrah Akyol; Mihaela van der Schaar 2007 IEEE International Conference on Image Processing, 2007

Significant power savings can be achieved on voltage/frequency configurable platforms by dynamically adapting the frequency and voltage according to the workload (complexity). Video decoding is one of the most complex tasks performed on such systems due to its computationally demanding operations like inverse filtering, interpolation, motion compensation and entropy decoding. Dynamically adapting the frequency and voltage for video decoding is ...


DVS for on-chip bus designs based on timing error correction

H. Kaul; D. Sylvester; D. Blaauw; T. Mudge; T. Austin Design, Automation and Test in Europe, 2005

On-chip buses are typically designed to meet performance constraints for worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern. This can result in significant performance slack at more typical operating conditions. We propose a dynamic voltage scaling (DVS) technique for buses, based on a double sampling latch which can detect and correct for delay errors without the ...


Temperature-Aware Scheduling: When is System-Throttling Good Enough?

Deepak Rajan; Philip S. Yu Web-Age Information Management, 2008. WAIM '08. The Ninth International Conference on, 2008

In computing centers, power-aware operating systems ensure that processor temperatures do not exceed a threshold by utilizing system-throttling. In this technique, the system load (or alternatively, the clock speed) is scaled when the temperature hits this threshold. At other times, the system operates at maximum load. In this paper, we show that such simple system-throttling rules are in fact the ...


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IEEE-USA E-Books

  • Design of Low Dropout (LDO) Regulators

    Low dropout (LDO) regulators are widely used in portable electronic devices because they occupy small chip and printed circuit board (PCB) areas. These regulators are appropriate for low-power applications because of heat dissipation. This chapter first introduces the basic LDO regulator, and then, presents concerns over compensation for loop stability to develop dominant pole compensation and C-free structures, which involves a dominant pole generated by Miller compensation capacitance. It also illustrates design flow and tips to understand the specifications and performance in analog LDO (A-LDO) regulators. The characteristics of A-LDO and digital LDO (D-LDO) regulators are then discussed and compared. LDO regulators with specific features are introduced to satisfy the requirements of various applications. Finally, the chapter introduces low-power techniques, including novel dynamic- voltage scaling (DVS) and analog DVS (ADVS), for compatible utilization in Soc applications.



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