Dynamic voltage scaling
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)
technology, architecture, circuits, tools, systems, software and applications
A-SSCC 2012 is an international forum for presenting the most updated and advanced chips and circuit designs in solid-state and semiconductor fields.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Fundamental technologies used in the control and conversion of electric power. Topics include dc-to- dc converter design, direct off-line switching power supplies, inverters, controlled rectifiers, control techniques, modeling, analysis and simulation techniques, the application of power circuit components (power semiconductors, magnetics, capacitors), and thermal performance of electronic power systems.
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...
Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.
Gang Quan; Linwei Niu; Hu, X.S.; Mochocki, B. Real-Time Systems Symposium, 2004. Proceedings. 25th IEEE International, 2004
While dynamic voltage scaling (DVS) is an efficient technique in reducing the dynamic energy consumption of a CMOS processor, methods that employ DVS without considering leakage current are quickly becoming less efficient when considering the processor's overall energy consumption. A leakage conscious DVS voltage schedule may require the processor to run at a higher-than- necessary speed to execute a given ...
Cheol-Hoon Lee; Shin, K.G. Real-Time Systems Symposium, 2004. Proceedings. 25th IEEE International, 2004
Recently, there has been a rapid and wide spread of non-traditional computing platforms, especially mobile and portable computing devices. As applications become sophisticated and computation power increases, the most serious limitation on these devices is the available battery life. Dynamic voltage scaling (DVS) has been a key technique to exploit the hardware characteristics of processors to reduce energy dissipation by ...
Magklis, G.; Chaparro, P.; Gonzalez, J.; Gonzalez, A. Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on, 2006
In recent years, globally asynchronous locally synchronous (GALS) designs and dynamic voltage scaling (DVS) have emerged as some of the most popular approaches to address the ever increasing microprocessor energy consumption. In this work, we propose two on-line algorithms for adjusting dynamically, and independently, the voltage and frequency of the front-end and back-end domains of a novel two-domain microprocessor. We ...
Mohan, N.; Sachdev, M. Electrical and Computer Engineering, 2004. Canadian Conference on, 2004
Ternary content addressable memories (TCAMs) are attractive for high-speed packet forwarding and classification in network switches and routers. Traditionally, the static power in TCAMs has been a small fraction of the total power due to high activity of TCAMs. However, technology scaling and architecture level techniques are reducing the dynamic power of TCAMs. The technology scaling is also increasing the ...
Ernst, D.; Das, S.; Seokwoo Lee; Blaauw, D.; Austin, T.; Mudge, T.; Nam Sung Kim; Flautner, K. Micro, IEEE, 2004
Dynamic voltage scaling is one of the more effective and widely used methods for power-aware computing. We present a DVS approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage margins
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