IEEE Organizations related to Drain avalanche hot carrier injection

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Conferences related to Drain avalanche hot carrier injection

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2013 IEEE International Integrated Reliability Workshop (IIRW)

We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits,systems, processes), customer product reliability requirements / manufacturer reliability tasks, waferlevel reliability tests (test approaches and reliability test structures), reliability modeling and simulation,optoelectronics, and single event upsets.

  • 2012 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.

  • 2011 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems through tutorials, paper presentations, discussion groups and special interest groups.

  • 2010 IEEE International Integrated Reliability Workshop (IIRW)

    The Integrated Reliability Workshop focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and f

  • 2009 IEEE International Integrated Reliability Workshop (IRW)

    Semiconductor Reliability in general; and Wafer Level Reliability in specific. Covering areas like (but not limited to): Design-in Reliability, reliability characterization, deep sub-micron transistor and circuit reliability, customer reliability requirements, wafer level reliability tests, and reliability root cause analysis, etc.

  • 2008 IEEE International Integrated Reliability Workshop (IRW)

    The workshop focuses on ensuring device reliability through fabrication, design, testing, characterization and simulation as well as identification of the defects and mechanisms responsible for reliability problems. It provides a unique environment for understanding, developing and sharing reliability technology and test methodology.

  • 2007 IEEE International Integrated Reliability Workshop (IRW)

    The Workshop focuses on ensuring semiconductor reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliabilty problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding and developing reliability technology and test methodology.

  • 2006 IEEE International Integrated Reliability Workshop (IRW)

  • 2005 IEEE International Integrated Reliability Workshop (IRW)



Periodicals related to Drain avalanche hot carrier injection

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.



Most published Xplore authors for Drain avalanche hot carrier injection

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Xplore Articles related to Drain avalanche hot carrier injection

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A Model of Human Decisionmaking in Fault Diagnosis Tasks That Include Feedback and Redundancy

Systems, Man and Cybernetics, IEEE Transactions on, 1979

None


Canonical forms for multi-input/multi-output minimal systems

Budin, M. Automatic Control, IEEE Transactions on, 1972

This correspondence presents an explicit discussion of the canonical forms for multi-input/multi-output minimal systems that are implicit in [1, eq. (13)-(20)]. The obvious advantage of these canonical forms is that they have the fewest free parameters. This becomes computationally significant in various parameter identification procedures.


Accelerated Negative-Bias Temperature Degradation in Low-Temperature Polycrystalline-Silicon p-Channel TFTs Under Dynamic Stress

Toyota, Y.; Matsumura, M.; Hatano, Mutsuko; Shiba, T.; Ohkura, M. Electron Devices, IEEE Transactions on, 2007

The degradation mechanism in p-channel polysilicon thin-film transistors under negative-bias temperature (NBT) stress and pulse stress, which alternates NBT stress and drain-avalanche hot carrier (DAHC) stress, was investigated. An analysis of recovery effects and activation energy suggests that the device degradation under dc-NBT stress is explained by a reaction-diffusion model and limited by hydrogen diffusion. These features are also observed ...


Hot Carrier Degradation Mechanism Under Pulsed Stress in Mosfets

Nagai, R.; Umeda, K.; Takeda, E. VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on, 1991

First Page of the Article ![](/xploreAssets/images/absImages/00705967.png)


A Model for Control Structures for Artificial Intelligence Programming Languages

Bobrow, D.G.; Wegbreit, B. Computers, IEEE Transactions on, 1976

Newer programming languages for artificial intelligence extend the class of available control regimes beyond simple hierarchical control. In so doing, a key issue is using a model that clearly exhibits the relation between modules, processes, access environments, and control environments. This paper presents a model which is applicable to diverse languages and presents a set of control primitives which provide ...


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Educational Resources on Drain avalanche hot carrier injection

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A Model of Human Decisionmaking in Fault Diagnosis Tasks That Include Feedback and Redundancy

Systems, Man and Cybernetics, IEEE Transactions on, 1979

None


Canonical forms for multi-input/multi-output minimal systems

Budin, M. Automatic Control, IEEE Transactions on, 1972

This correspondence presents an explicit discussion of the canonical forms for multi-input/multi-output minimal systems that are implicit in [1, eq. (13)-(20)]. The obvious advantage of these canonical forms is that they have the fewest free parameters. This becomes computationally significant in various parameter identification procedures.


Accelerated Negative-Bias Temperature Degradation in Low-Temperature Polycrystalline-Silicon p-Channel TFTs Under Dynamic Stress

Toyota, Y.; Matsumura, M.; Hatano, Mutsuko; Shiba, T.; Ohkura, M. Electron Devices, IEEE Transactions on, 2007

The degradation mechanism in p-channel polysilicon thin-film transistors under negative-bias temperature (NBT) stress and pulse stress, which alternates NBT stress and drain-avalanche hot carrier (DAHC) stress, was investigated. An analysis of recovery effects and activation energy suggests that the device degradation under dc-NBT stress is explained by a reaction-diffusion model and limited by hydrogen diffusion. These features are also observed ...


Hot Carrier Degradation Mechanism Under Pulsed Stress in Mosfets

Nagai, R.; Umeda, K.; Takeda, E. VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on, 1991

First Page of the Article ![](/xploreAssets/images/absImages/00705967.png)


A Model for Control Structures for Artificial Intelligence Programming Languages

Bobrow, D.G.; Wegbreit, B. Computers, IEEE Transactions on, 1976

Newer programming languages for artificial intelligence extend the class of available control regimes beyond simple hierarchical control. In so doing, a key issue is using a model that clearly exhibits the relation between modules, processes, access environments, and control environments. This paper presents a model which is applicable to diverse languages and presents a set of control primitives which provide ...


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