IEEE Organizations related to Drain avalanche hot carrier injection

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Conferences related to Drain avalanche hot carrier injection

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2013 IEEE International Integrated Reliability Workshop (IIRW)

We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits,systems, processes), customer product reliability requirements / manufacturer reliability tasks, waferlevel reliability tests (test approaches and reliability test structures), reliability modeling and simulation,optoelectronics, and single event upsets.

  • 2012 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.

  • 2011 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems through tutorials, paper presentations, discussion groups and special interest groups.

  • 2010 IEEE International Integrated Reliability Workshop (IIRW)

    The Integrated Reliability Workshop focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and f

  • 2009 IEEE International Integrated Reliability Workshop (IRW)

    Semiconductor Reliability in general; and Wafer Level Reliability in specific. Covering areas like (but not limited to): Design-in Reliability, reliability characterization, deep sub-micron transistor and circuit reliability, customer reliability requirements, wafer level reliability tests, and reliability root cause analysis, etc.

  • 2008 IEEE International Integrated Reliability Workshop (IRW)

    The workshop focuses on ensuring device reliability through fabrication, design, testing, characterization and simulation as well as identification of the defects and mechanisms responsible for reliability problems. It provides a unique environment for understanding, developing and sharing reliability technology and test methodology.

  • 2007 IEEE International Integrated Reliability Workshop (IRW)

    The Workshop focuses on ensuring semiconductor reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliabilty problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding and developing reliability technology and test methodology.

  • 2006 IEEE International Integrated Reliability Workshop (IRW)

  • 2005 IEEE International Integrated Reliability Workshop (IRW)



Periodicals related to Drain avalanche hot carrier injection

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.



Most published Xplore authors for Drain avalanche hot carrier injection

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Xplore Articles related to Drain avalanche hot carrier injection

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TCAD driven drain engineering for hot carrier reduction of 3.3V I/O p-MOSFET

Miura, N.; Hayashi, H.; Komatsubara, H.; Mochizuki, M.; Fukuda, K. Simulation of Semiconductor Processes and Devices, 2002. SISPAD 2002. International Conference on, 2002

We present a TCAD driven hot carrier reduction methodology of 3.3V I/O p-MOSFETs design. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and ION, HALO/SDE of both core and I/O transistors can be totally optimized for photo-mask reduction.


Characterization of back-channel subthreshold conduction of walled SOI devices

Chen, H.; Yue, J.; Dougal, G. Electron Devices, IEEE Transactions on, 1991

Summary form only given. Submicrometer CMOS transistors with junctions walled to a trenched isolation oxide have been fabricated on SIMOX substrates. Back- channel leakage of the devices was measured as a function of substrate bias. Compared with nonwalled devices, walled devices showed early turn-on of the back-channel at relatively low substrate biases. This phenomenon is caused by the two-dimensional electrical ...


Hot-carrier-resistant structure by Re-oxidized nitrided oxide sidewall for highly reliable and high performance LDD MOSFETs

Kusunoki, S.; Inuishi, M.; Yamaguchi, T.; Tsukamoto, K.; Akasaka, Y. Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International, 1991

The authors have proposed a novel structure which satisfies both high performance and high reliability with re-oxidized nitrided oxide (RNO) film in the sidewall of the LDD (lightly doped drain) transistor using rapid thermal nitridation (RTN). With this structure, the hot-carrier resistance of the LDD can be improved without the degradation of mobility as seen in MOSFETs having the RNO ...


A likelihood ratio formula for two-dimensional random fields

Wong, E. Information Theory, IEEE Transactions on, 1974

This paper is concerned with the detection of a random signal in white Gaussian noise when both the signal and the noise are two-dimensional random fields. The principal result is the derivation of a recursive formula for the likelihood ratio relating it to certain conditional moments of the signal. It is also shown that, except for some relatively uninteresting cases, ...


Investigation to suppress hot carrier effect in pocket-implanted nMOSFET by full band Monte Carlo simulation

Tanaka, T.; Yamaguchi, S.; Yamaguchi, S.; Sukegawa, K.; Goto, H. Computational Electronics, 1998. IWCE-6. Extended Abstracts of 1998 Sixth International Workshop on, 1998

We have clarified two dimensional hot carrier (HC) properties of pocket implanted nMOSFETs by full band Monte Carlo device simulation, and we have shown that the HC generation can be suppressed, keeping better V/sub th/ roll- off, without deterioration of driving capability by properly choosing the pocket implant tilt angle. We have also confirmed this by measurements of gate and ...


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Educational Resources on Drain avalanche hot carrier injection

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eLearning

TCAD driven drain engineering for hot carrier reduction of 3.3V I/O p-MOSFET

Miura, N.; Hayashi, H.; Komatsubara, H.; Mochizuki, M.; Fukuda, K. Simulation of Semiconductor Processes and Devices, 2002. SISPAD 2002. International Conference on, 2002

We present a TCAD driven hot carrier reduction methodology of 3.3V I/O p-MOSFETs design. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and ION, HALO/SDE of both core and I/O transistors can be totally optimized for photo-mask reduction.


Characterization of back-channel subthreshold conduction of walled SOI devices

Chen, H.; Yue, J.; Dougal, G. Electron Devices, IEEE Transactions on, 1991

Summary form only given. Submicrometer CMOS transistors with junctions walled to a trenched isolation oxide have been fabricated on SIMOX substrates. Back- channel leakage of the devices was measured as a function of substrate bias. Compared with nonwalled devices, walled devices showed early turn-on of the back-channel at relatively low substrate biases. This phenomenon is caused by the two-dimensional electrical ...


Hot-carrier-resistant structure by Re-oxidized nitrided oxide sidewall for highly reliable and high performance LDD MOSFETs

Kusunoki, S.; Inuishi, M.; Yamaguchi, T.; Tsukamoto, K.; Akasaka, Y. Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International, 1991

The authors have proposed a novel structure which satisfies both high performance and high reliability with re-oxidized nitrided oxide (RNO) film in the sidewall of the LDD (lightly doped drain) transistor using rapid thermal nitridation (RTN). With this structure, the hot-carrier resistance of the LDD can be improved without the degradation of mobility as seen in MOSFETs having the RNO ...


A likelihood ratio formula for two-dimensional random fields

Wong, E. Information Theory, IEEE Transactions on, 1974

This paper is concerned with the detection of a random signal in white Gaussian noise when both the signal and the noise are two-dimensional random fields. The principal result is the derivation of a recursive formula for the likelihood ratio relating it to certain conditional moments of the signal. It is also shown that, except for some relatively uninteresting cases, ...


Investigation to suppress hot carrier effect in pocket-implanted nMOSFET by full band Monte Carlo simulation

Tanaka, T.; Yamaguchi, S.; Yamaguchi, S.; Sukegawa, K.; Goto, H. Computational Electronics, 1998. IWCE-6. Extended Abstracts of 1998 Sixth International Workshop on, 1998

We have clarified two dimensional hot carrier (HC) properties of pocket implanted nMOSFETs by full band Monte Carlo device simulation, and we have shown that the HC generation can be suppressed, keeping better V/sub th/ roll- off, without deterioration of driving capability by properly choosing the pocket implant tilt angle. We have also confirmed this by measurements of gate and ...


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