IEEE Organizations related to Drain avalanche hot carrier injection

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Conferences related to Drain avalanche hot carrier injection

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2013 IEEE International Integrated Reliability Workshop (IIRW)

We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits,systems, processes), customer product reliability requirements / manufacturer reliability tasks, waferlevel reliability tests (test approaches and reliability test structures), reliability modeling and simulation,optoelectronics, and single event upsets.

  • 2012 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.

  • 2011 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems through tutorials, paper presentations, discussion groups and special interest groups.

  • 2010 IEEE International Integrated Reliability Workshop (IIRW)

    The Integrated Reliability Workshop focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and f

  • 2009 IEEE International Integrated Reliability Workshop (IRW)

    Semiconductor Reliability in general; and Wafer Level Reliability in specific. Covering areas like (but not limited to): Design-in Reliability, reliability characterization, deep sub-micron transistor and circuit reliability, customer reliability requirements, wafer level reliability tests, and reliability root cause analysis, etc.

  • 2008 IEEE International Integrated Reliability Workshop (IRW)

    The workshop focuses on ensuring device reliability through fabrication, design, testing, characterization and simulation as well as identification of the defects and mechanisms responsible for reliability problems. It provides a unique environment for understanding, developing and sharing reliability technology and test methodology.

  • 2007 IEEE International Integrated Reliability Workshop (IRW)

    The Workshop focuses on ensuring semiconductor reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliabilty problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding and developing reliability technology and test methodology.

  • 2006 IEEE International Integrated Reliability Workshop (IRW)

  • 2005 IEEE International Integrated Reliability Workshop (IRW)



Periodicals related to Drain avalanche hot carrier injection

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.



Most published Xplore authors for Drain avalanche hot carrier injection

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Xplore Articles related to Drain avalanche hot carrier injection

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The Design of Minimum-Cost Survivable Networks

K. Steiglitz; P. Weiner; D. Kleitman IEEE Transactions on Circuit Theory, 1969

We consider the problem of designing a network which satisfies a prespecified survivability criterion with minimum cost. The survivability criterion demands that there be at least ![r_{ij}](/images/tex/11038.gif) node disjoint paths between nodes ![i](/images/tex/1068.gif) and ![j](/images/tex/1046.gif) , where ![(r_{ij})](/images/tex/11039.gif) is a given redundancy requirement matrix. This design problem appears to be at least as difficult as the traveling salesman problem, and ...


On the Topological Design of Distributed Computer Networks

M. Gerla; L. Kleinrock IEEE Transactions on Communications, 1977

The problem of data transmission in a network environment involves the design of a communication subnetwork. Recently, significant progress has been made in this technology, and in this article we survey the modeling, analysis, and design of such computercommunication networks. Most of the design methodology presented has been developed with the packet-switched Advanced Research Projects Agency Network (ARPANET) in mind, ...


Accelerated Negative-Bias Temperature Degradation in Low-Temperature Polycrystalline-Silicon p-Channel TFTs Under Dynamic Stress

Yoshiaki Toyota; Mieko Matsumura; Mutsuko Hatano; Takeo Shiba; Makoto Ohkura IEEE Transactions on Electron Devices, 2007

The degradation mechanism in p-channel polysilicon thin-film transistors under negative-bias temperature (NBT) stress and pulse stress, which alternates NBT stress and drain-avalanche hot carrier (DAHC) stress, was investigated. An analysis of recovery effects and activation energy suggests that the device degradation under dc-NBT stress is explained by a reaction-diffusion model and limited by hydrogen diffusion. These features are also observed ...


New hot-carrier degradation mode in PMOSFETs with W gate electrodes

H. Matsuhashi; T. Hayashi; S. Nishikawa IEEE Electron Device Letters, 1991

Hot-carrier degradation of W gate PMOSFETs, which are surface-channel devices because of the work function of W, has been investigated in comparison with polycide (WSi/sub x//n/sup +/ poly-Si) ones. In W gate PMOSFETs, transconductance g/sub m/ and threshold voltage V/sub th/ decrease on the drain avalanche hot-carrier (DAHC) stress, and Delta g/sub m//g/sub m0/ and Delta V/sub th/ become minimum ...


A Novel Substrate Hot Electron and Hole Injection Structure with a Double Implanted Buried Channel Mosfet

Sukvoon Yoon; R. Siergiej; M. H. White [1991] 49th Annual Device Research Conference Digest, 1991

First Page of the Article ![](/xploreAssets/images/absImages/00664731.png)


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Educational Resources on Drain avalanche hot carrier injection

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eLearning

A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under AC stress

Electron Devices, IEEE Transactions on, 2004

Enhanced device degradation of low-temperature n-channel polycrystalline thin- film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater ...


A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection

Electron Device Letters, IEEE, 1995

A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate flash EEPROM's. By lowering the drain voltage and increasing the magnitude of the negative substrate bias voltage, the substrate current is reduced but the hot electron gate current is enhanced significantly, and the convergence time is shown ...


Experimental evidence for nonlucky electron model effect in 0.15-μm NMOSFETs

Electron Devices, IEEE Transactions on, 2002

It is shown that in 0.15-μm NMOSFETs the device lifetime under channel hot- carrier (CHC) stress is lower than that under drain avalanche hot-carrier (DAHC) stress and therefore the hot-carrier stress-induced device degradation in 0.15-μm NMOSFETs cannot be explained in the framework of the lucky electron model (LEM). Our investigation suggests that such a "non-LEM effect" may be due to ...


Mechanism of device degradation under AC stress in low-temperature polycrystalline silicon TFTs

Reliability Physics Symposium Proceedings, 2002. 40th Annual, 2002

Enhanced device degradation of low-temperature polycrystalline thin-film transistors (poly-Si TFTs) under exposure to AC stress has been quantitatively analyzed. Degradation of the device characteristics of a single-drain (SD) TFT is greater under AC stress than under DC stress over an equivalent period. Hot holes are strongly related to this greater severity of degradation. A lightly doped drain (LDD) TFT is ...


A novel substrate hot electron and hole injection structure with a double-implanted buried-channel MOSFET

Electron Devices, IEEE Transactions on, 1991

Summary form only given. Substrate hot electron and hole injection into the same gate insulator is achieved with a double ion-implanted buried-channel n-channel MOSFET device. Under the gate, the impurity profile is n-on-n+ on a p substrate. The n-on-n+ buried channel, which is formed by implanting the phosphorus ions twice (first, deep heavy implant and, second, shallow and light implant), ...


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