IEEE Organizations related to Drain avalanche hot carrier injection

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Conferences related to Drain avalanche hot carrier injection

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2013 IEEE International Integrated Reliability Workshop (IIRW)

We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits,systems, processes), customer product reliability requirements / manufacturer reliability tasks, waferlevel reliability tests (test approaches and reliability test structures), reliability modeling and simulation,optoelectronics, and single event upsets.

  • 2012 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.

  • 2011 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems through tutorials, paper presentations, discussion groups and special interest groups.

  • 2010 IEEE International Integrated Reliability Workshop (IIRW)

    The Integrated Reliability Workshop focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and f

  • 2009 IEEE International Integrated Reliability Workshop (IRW)

    Semiconductor Reliability in general; and Wafer Level Reliability in specific. Covering areas like (but not limited to): Design-in Reliability, reliability characterization, deep sub-micron transistor and circuit reliability, customer reliability requirements, wafer level reliability tests, and reliability root cause analysis, etc.

  • 2008 IEEE International Integrated Reliability Workshop (IRW)

    The workshop focuses on ensuring device reliability through fabrication, design, testing, characterization and simulation as well as identification of the defects and mechanisms responsible for reliability problems. It provides a unique environment for understanding, developing and sharing reliability technology and test methodology.

  • 2007 IEEE International Integrated Reliability Workshop (IRW)

    The Workshop focuses on ensuring semiconductor reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliabilty problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding and developing reliability technology and test methodology.

  • 2006 IEEE International Integrated Reliability Workshop (IRW)

  • 2005 IEEE International Integrated Reliability Workshop (IRW)



Periodicals related to Drain avalanche hot carrier injection

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.



Most published Xplore authors for Drain avalanche hot carrier injection

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Xplore Articles related to Drain avalanche hot carrier injection

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A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection

C. -Y. Hu; D. L. Kencke; S. K. Banerjee; R. Richart; B. Bandyopadhyay; B. Moore; E. Ibok; S. Garg IEEE Electron Device Letters, 1995

A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate flash EEPROM's. By lowering the drain voltage and increasing the magnitude of the negative substrate bias voltage, the substrate current is reduced but the hot electron gate current is enhanced significantly, and the convergence time is shown ...


In-Line Monitoring of Hot Carrier Lifetime and Its Dependency on Process Parameter for Submicron High Density DRAM Manufacturing

S. C. Hong; D. H. Shin; W. Lee; B. I. Ryu; H. K. Chung International Integrated Reliability Workshop Final Report, 1993

First Page of the Article ![](/xploreAssets/images/absImages/00666323.png)


High-frequency fields excited by a line source located on a perfectly conducting concave cylindrical surface

T. Ishihara; L. Felsen; A. Green IEEE Transactions on Antennas and Propagation, 1978

Alternative representations are obtained for the high-frequency surface field excited on a perfectly conducting concave circular cylinder by an axial magnetic line current located on the surface. Included are ray-optical, canonical integral, whispering gallery mode, and near-field formulations, and various combinations of these. Asymptotic evaluations in different parameter ranges lead to results with varying accuracy and physical content. Their utility ...


On the Ordering of Connections for Automatic Wire Routing

L. C. Abel IEEE Transactions on Computers, 1972

Most wire-routing programs utilize a maze-running technique to route one connection at a time. Once routed, a wire cannot be moved even if it is subsequently discovered to interfere with the successful completion of other connections. The order in which the desired connections are presented to the routing algorithm has therefore been thought to be of critical importance. Experimental evidence ...


A preliminary investigation of a neocortex model implementation on the Cray XD1

Kenneth L. Rice; Christopher N. Vutsinas; Tarek M. Taha SC '07: Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, 2007

In this paper we study the acceleration of a new class of cognitive processing applications based on the structure of the neocortex. Specifically we examine the speedup of a visual cortex model for image recognition. We propose techniques to accelerate the application on general purpose processors and on reconfigurable logic. We present implementations of our approach on a Cray XD1 ...


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Educational Resources on Drain avalanche hot carrier injection

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eLearning

A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection

C. -Y. Hu; D. L. Kencke; S. K. Banerjee; R. Richart; B. Bandyopadhyay; B. Moore; E. Ibok; S. Garg IEEE Electron Device Letters, 1995

A novel convergence scheme using substrate-bias-enhanced hot electron injection is proposed to tighten the cell threshold voltage distribution after erasure for stacked gate flash EEPROM's. By lowering the drain voltage and increasing the magnitude of the negative substrate bias voltage, the substrate current is reduced but the hot electron gate current is enhanced significantly, and the convergence time is shown ...


In-Line Monitoring of Hot Carrier Lifetime and Its Dependency on Process Parameter for Submicron High Density DRAM Manufacturing

S. C. Hong; D. H. Shin; W. Lee; B. I. Ryu; H. K. Chung International Integrated Reliability Workshop Final Report, 1993

First Page of the Article ![](/xploreAssets/images/absImages/00666323.png)


High-frequency fields excited by a line source located on a perfectly conducting concave cylindrical surface

T. Ishihara; L. Felsen; A. Green IEEE Transactions on Antennas and Propagation, 1978

Alternative representations are obtained for the high-frequency surface field excited on a perfectly conducting concave circular cylinder by an axial magnetic line current located on the surface. Included are ray-optical, canonical integral, whispering gallery mode, and near-field formulations, and various combinations of these. Asymptotic evaluations in different parameter ranges lead to results with varying accuracy and physical content. Their utility ...


On the Ordering of Connections for Automatic Wire Routing

L. C. Abel IEEE Transactions on Computers, 1972

Most wire-routing programs utilize a maze-running technique to route one connection at a time. Once routed, a wire cannot be moved even if it is subsequently discovered to interfere with the successful completion of other connections. The order in which the desired connections are presented to the routing algorithm has therefore been thought to be of critical importance. Experimental evidence ...


A preliminary investigation of a neocortex model implementation on the Cray XD1

Kenneth L. Rice; Christopher N. Vutsinas; Tarek M. Taha SC '07: Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, 2007

In this paper we study the acceleration of a new class of cognitive processing applications based on the structure of the neocortex. Specifically we examine the speedup of a visual cortex model for image recognition. We propose techniques to accelerate the application on general purpose processors and on reconfigurable logic. We present implementations of our approach on a Cray XD1 ...


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