IEEE Organizations related to Drain avalanche hot carrier injection

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Conferences related to Drain avalanche hot carrier injection

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2013 IEEE International Integrated Reliability Workshop (IIRW)

We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits,systems, processes), customer product reliability requirements / manufacturer reliability tasks, waferlevel reliability tests (test approaches and reliability test structures), reliability modeling and simulation,optoelectronics, and single event upsets.

  • 2012 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.

  • 2011 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems through tutorials, paper presentations, discussion groups and special interest groups.

  • 2010 IEEE International Integrated Reliability Workshop (IIRW)

    The Integrated Reliability Workshop focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and f

  • 2009 IEEE International Integrated Reliability Workshop (IRW)

    Semiconductor Reliability in general; and Wafer Level Reliability in specific. Covering areas like (but not limited to): Design-in Reliability, reliability characterization, deep sub-micron transistor and circuit reliability, customer reliability requirements, wafer level reliability tests, and reliability root cause analysis, etc.

  • 2008 IEEE International Integrated Reliability Workshop (IRW)

    The workshop focuses on ensuring device reliability through fabrication, design, testing, characterization and simulation as well as identification of the defects and mechanisms responsible for reliability problems. It provides a unique environment for understanding, developing and sharing reliability technology and test methodology.

  • 2007 IEEE International Integrated Reliability Workshop (IRW)

    The Workshop focuses on ensuring semiconductor reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliabilty problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding and developing reliability technology and test methodology.

  • 2006 IEEE International Integrated Reliability Workshop (IRW)

  • 2005 IEEE International Integrated Reliability Workshop (IRW)



Periodicals related to Drain avalanche hot carrier injection

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.



Most published Xplore authors for Drain avalanche hot carrier injection

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Xplore Articles related to Drain avalanche hot carrier injection

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A comprehensive methodology and model for the characterization of hot-carrier induced MOS device degradation

Waisum Wong; A. Icel Proceedings of First International Caracas Conference on Devices, Circuits and Systems, 1995

One of the main concerns in the submicron MOS technologies is the device lifetime associated with the hot carrier injection into the gate oxide due to the high electric fields on the drain/source terminals or across the channel. Many previous works have been devoted to the MOS device degradation theory and the lifetime prediction. This paper, on the other hand, ...


A Model for Control Structures for Artificial Intelligence Programming Languages

D. G. Bobrow; B. Wegbreit IEEE Transactions on Computers, 1976

Newer programming languages for artificial intelligence extend the class of available control regimes beyond simple hierarchical control. In so doing, a key issue is using a model that clearly exhibits the relation between modules, processes, access environments, and control environments. This paper presents a model which is applicable to diverse languages and presents a set of control primitives which provide ...


Age-based packet arbitration in large-radix k-ary n-cubes

Dennis Abts; Deborah Weisser SC '07: Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, 2007

As applications scale to increasingly large processor counts, the interconnection network is frequently the limiting factor in application performance. In order to achieve application scalability, the interconnect must maintain high bandwidth while minimizing variation in packet latency. As the offered load in the network increases with growing problem sizes and processor counts, so does the expected maximum packet latency in ...


A novel substrate hot electron and hole injection structure with a double-implanted buried-channel MOSFET

S. Yoon; R. Siergiej; M. H. White IEEE Transactions on Electron Devices, 1991

Summary form only given. Substrate hot electron and hole injection into the same gate insulator is achieved with a double ion-implanted buried-channel n-channel MOSFET device. Under the gate, the impurity profile is n-on-n+ on a p substrate. The n-on-n+ buried channel, which is formed by implanting the phosphorus ions twice (first, deep heavy implant and, second, shallow and light implant), ...


Data access history cache and associated data prefetching mechanisms

Yong Chen; Surendra Byna; Xian-He Sun SC '07: Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, 2007

Data prefetching is an effective way to bridge the increasing performance gap between processor and memory. As computing power is increasing much faster than memory performance, we suggest that it is time to have a dedicated cache to store data access histories and to serve prefetching to mask data access latency effectively. We thus propose a new cache structure, named ...


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Educational Resources on Drain avalanche hot carrier injection

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eLearning

A comprehensive methodology and model for the characterization of hot-carrier induced MOS device degradation

Waisum Wong; A. Icel Proceedings of First International Caracas Conference on Devices, Circuits and Systems, 1995

One of the main concerns in the submicron MOS technologies is the device lifetime associated with the hot carrier injection into the gate oxide due to the high electric fields on the drain/source terminals or across the channel. Many previous works have been devoted to the MOS device degradation theory and the lifetime prediction. This paper, on the other hand, ...


A Model for Control Structures for Artificial Intelligence Programming Languages

D. G. Bobrow; B. Wegbreit IEEE Transactions on Computers, 1976

Newer programming languages for artificial intelligence extend the class of available control regimes beyond simple hierarchical control. In so doing, a key issue is using a model that clearly exhibits the relation between modules, processes, access environments, and control environments. This paper presents a model which is applicable to diverse languages and presents a set of control primitives which provide ...


Age-based packet arbitration in large-radix k-ary n-cubes

Dennis Abts; Deborah Weisser SC '07: Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, 2007

As applications scale to increasingly large processor counts, the interconnection network is frequently the limiting factor in application performance. In order to achieve application scalability, the interconnect must maintain high bandwidth while minimizing variation in packet latency. As the offered load in the network increases with growing problem sizes and processor counts, so does the expected maximum packet latency in ...


A novel substrate hot electron and hole injection structure with a double-implanted buried-channel MOSFET

S. Yoon; R. Siergiej; M. H. White IEEE Transactions on Electron Devices, 1991

Summary form only given. Substrate hot electron and hole injection into the same gate insulator is achieved with a double ion-implanted buried-channel n-channel MOSFET device. Under the gate, the impurity profile is n-on-n+ on a p substrate. The n-on-n+ buried channel, which is formed by implanting the phosphorus ions twice (first, deep heavy implant and, second, shallow and light implant), ...


Data access history cache and associated data prefetching mechanisms

Yong Chen; Surendra Byna; Xian-He Sun SC '07: Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, 2007

Data prefetching is an effective way to bridge the increasing performance gap between processor and memory. As computing power is increasing much faster than memory performance, we suggest that it is time to have a dedicated cache to store data access histories and to serve prefetching to mask data access latency effectively. We thus propose a new cache structure, named ...


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