Drain avalanche hot carrier injection
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2013 IEEE International Integrated Reliability Workshop (IIRW)
We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits,systems, processes), customer product reliability requirements / manufacturer reliability tasks, waferlevel reliability tests (test approaches and reliability test structures), reliability modeling and simulation,optoelectronics, and single event upsets.
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Ott, M.; Zola, J.; Stamatakis, A.; Aluru, S. Supercomputing, 2007. SC '07. Proceedings of the 2007 ACM/IEEE Conference on, 2007
Phylogenetic inference is a grand challenge in Bioinformatics due to immense computational requirements. The increasing popularity of multi-gene alignments in biological studies, which typically provide a stable topological signal due to a more favorable ratio of the number of base pairs to the number of sequences, coupled with rapid accumulation of sequence data in general, poses new challenges for high ...
Abts, D.; Weisser, Deborah Supercomputing, 2007. SC '07. Proceedings of the 2007 ACM/IEEE Conference on, 2007
As applications scale to increasingly large processor counts, the interconnection network is frequently the limiting factor in application performance. In order to achieve application scalability, the interconnect must maintain high bandwidth while minimizing variation in packet latency. As the offered load in the network increases with growing problem sizes and processor counts, so does the expected maximum packet latency in ...
Sang-Gi Lee; Hwang, Jeong-Mo; Hi-Deok Lee Electron Devices, IEEE Transactions on, 2002
It is shown that in 0.15-μm NMOSFETs the device lifetime under channel hot- carrier (CHC) stress is lower than that under drain avalanche hot-carrier (DAHC) stress and therefore the hot-carrier stress-induced device degradation in 0.15-μm NMOSFETs cannot be explained in the framework of the lucky electron model (LEM). Our investigation suggests that such a "non-LEM effect" may be due to ...
Sugiharto, D.S.; Yang, Cary Y.; Huy Le; Chung, J.E. Circuits and Devices Magazine, IEEE, 1998
CMOS hot-carrier reliability at both transistor and circuit levels has been examined. Accurate reliability assessment requires defining suitable criteria for acceptable performance for both circuit and individual transistors. As device designers meet demands for greater speed and more complex circuitry accompanied by shrinking the size of transistor into the deep-submicron regime, they have to contend with increase in current densities ...
Koike, N.; Tatsuuma, K. Device and Materials Reliability, IEEE Transactions on, 2004
A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as τ(Id/W)2∝(Isub/Id)-m. The formula is different from the conventional τId/W-Isub/Id model in that the exponent of Id/W is 2, which results from the ...
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