Drain avalanche hot carrier injection
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2013 IEEE International Integrated Reliability Workshop (IIRW)
We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliab
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Takeda, E.; Nakagome, Y.; Kume, H.; Asai, S. Solid-State and Electron Devices, IEE Proceedings I, 1983
New kinds of hot-carrier injection mechanisms, which are different from channel hot-electron and substrate hot-electron injection mechanisms already reported by Ning, et al., are presented. These are first drain avalanche hot- carrier (DAHC) injection and secondly substrate current induced hot-electron (SCHE) injection. DAHC injection is due to the emission of electrons and holes heated in the drain avalanche plasma. SCHE ...
Kusunoki, S.; Inuishi, M.; Yamaguchi, T.; Tsukamoto, K.; Akasaka, Y. Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International, 1991
The authors have proposed a novel structure which satisfies both high performance and high reliability with re-oxidized nitrided oxide (RNO) film in the sidewall of the LDD (lightly doped drain) transistor using rapid thermal nitridation (RTN). With this structure, the hot-carrier resistance of the LDD can be improved without the degradation of mobility as seen in MOSFETs having the RNO ...
Takeda, E.; Izawa, Ryuichi; Umeda, Kazunori; Nagai, R. Reliability Physics Symposium, 1991, 29th Annual Proceedings., International, 1991
AC hot-carrier effects with complete precautions against the wiring inductance noises were investigated to get a universal guideline from the viewpoints of AC conditions and device structures (single drain (SD), LDD, and GOLD). Pulse- induced-noises due to the wiring inductance of measurement systems screens intrinsic AC effects. After precautions against noises, AC hot-carrier degradation can be estimated in LDD on ...
Takeda, E.; Shimizu, A.; Hagiwara, T. Electron Device Letters, IEEE, 1983
Drain avalanche hot-carrier (DAHC) injection, which imposes the most severe limitations on n-channel MOS device design, is investigated from the viewpoint of surface-state generation and its localized area in the channel. It is shown, using the charge pumping technique, that the surface states are mainly created by hot-hole injection, and its small degraded area stretches toward the source region with ...
Miura, N.; Hayashi, H.; Komatsubara, H.; Mochizuki, M.; Fukuda, K. Simulation of Semiconductor Processes and Devices, 2002. SISPAD 2002. International Conference on, 2002
We present a TCAD driven hot carrier reduction methodology of 3.3V I/O p-MOSFETs design. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and ION, HALO/SDE of both core and I/O transistors can be totally optimized for photo-mask reduction.
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