Drain avalanche hot carrier injection
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2013 IEEE International Integrated Reliability Workshop (IIRW)
We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits,systems, processes), customer product reliability requirements / manufacturer reliability tasks, waferlevel reliability tests (test approaches and reliability test structures), reliability modeling and simulation,optoelectronics, and single event upsets.
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Systems, Man and Cybernetics, IEEE Transactions on, 1979
Toyota, Y.; Shiba, T.; Ohkura, M. Electron Devices, IEEE Transactions on, 2004
Enhanced device degradation of low-temperature n-channel polycrystalline thin- film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater ...
Kawamura, T.; Matsumura, M.; Kaitoh, T.; Noda, T.; Hatano, Mutsuko; Miyazawa, T.; Ohkura, M. Electron Devices, IEEE Transactions on, 2009
A model for predicting on-current degradation caused by drain-avalanche hot carriers in NMOS low-temperature polysilicon thin-film transistors (TFTs) is described. The amount of trapped charge caused by hot-carrier stress was estimated by using a model describing the lightly doped drain region as an imaginary TFT, and it was found that the amount of trapped charge saturates as voltage-stress time passes. ...
Koike, N.; Tatsuuma, K. Reliability Physics Symposium Proceedings, 2002. 40th Annual, 2002
A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as τ(Id/W)2∝(Isub/Id)-m. The formula is different from the conventional τId/W-Isub/Id model in that the exponent of Id/W is 2, which results from the ...
Sang-Gi Lee; Hwang, Jeong-Mo; Hi-Deok Lee Electron Devices, IEEE Transactions on, 2002
It is shown that in 0.15-μm NMOSFETs the device lifetime under channel hot- carrier (CHC) stress is lower than that under drain avalanche hot-carrier (DAHC) stress and therefore the hot-carrier stress-induced device degradation in 0.15-μm NMOSFETs cannot be explained in the framework of the lucky electron model (LEM). Our investigation suggests that such a "non-LEM effect" may be due to ...
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