Conferences related to Demultiplexing

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No conferences are currently tagged "Demultiplexing"


Periodicals related to Demultiplexing

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Lightwave Technology, Journal of

All aspects of optical guided-wave science, technology, and engineering in the areas of fiber and cable technologies; active and passive guided-wave componentry (light sources, detectors, repeaters, switches, fiber sensors, etc.); integrated optics and optoelectronics; systems and subsystems; new applications; and unique field trials.


Photonics Technology Letters, IEEE

Rapid publication of original research relevant to photonics technology. This expanding field emphasizes laser and electro-optic technology, laser physics and systems, applications, and photonic/ lightwave components and applications. The journal offers short, archival publication with minimal delay.



Most published Xplore authors for Demultiplexing

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Xplore Articles related to Demultiplexing

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Ultra-high-speed serial optical communications: Enabling technologies

L. K. Oxenlowe; M. Galili; H. C. H. Mulvad; H. Ji; A. T. Clausen; R. Kjaer; P. Jeppesen 2008 International Conference on Photonics in Switching, 2008

This paper will present recently identified and demonstrated key technologies for ultra-high-speed serial communications. Certain key components such as stabilised highly non-linear fibre switches, periodically poled Lithium Niobate devices and semiconductor optical amplifiers will be described with demonstrations of 640 Gb/s transmission, clock recovery, demultiplexing, add/drop, wavelength conversion and channel identification. Timing jitter tolerance is addressed through techniques to create ...


Highly nonlinear Chalcogenide waveguide devices for ultra-fast all-optical signal processing

M. D. Pelusi; F. Luan; E. C. Magi; M. R. E. Lamont; D. Moss; B. J. Eggleton; S. Madden; D. -Y. Choi; D. A. P. Bulla; B. Luther-Davies 2008 IEEE PhotonicsGlobal@Singapore, 2008

A review of the development and applications of compact highly nonlinear Chalcogenide waveguides for ultra-fast all-optical signal processing is presented. We demonstrate the extreme tapering of a highly nonlinear As2S3 fiber to further increase its nonlinearity by more than an order of magnitude thereby enabling time-division demultiplexing of a 160 Gb/s signal by four- wave mixing (FWM) with significantly lower ...


Low supply voltage operation of 40-Gb/s full-rate 4:1 multiplexer based on parallel-current-switching latch circuitry

Y. Amamiya; Y. Suzuki; Y. Yamazaki; M. Mamada; H. Hida IEEE Compound Semiconductor Integrated Circuit Symposium, 2004., 2004

We implemented new circuit topology, a parallel-current-switching latch, in a full-rate 4:1 multiplexer using InP-HBT technology. This is the first report of this technology, which resulted in 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. This voltage is as low as that of high-speed CMOS I/O circuits. This circuit topology ...


Design and Implementation of an MHP Video and Graphics Subsystem on Xilinx ML310 Platform

Min-hong Chen; Feng-cheng Chang; Hsueh-ming Hang 2006 International Conference on Intelligent Information Hiding and Multimedia, 2006

Multimedia Home Platform (MHP) is a standard to enable versatile applications of a DVB program. In this paper, we design and implement a simplified MHP video and graphics subsystem. The Xilinx ML310 is chosen as the hardware platform to implement our design. The execution environment consists of an embedded Linux, a frame-buffer based X server, and a Java ME Personal ...


A 622-Mb/s 8×8 ATM switch chip set with shared multibuffer architecture

H. Kondoh; H. Notani; H. Yamanaka; K. Higashitani; H. Saito; I. Hayashi; S. Kohama; Y. Matsuda; K. Oshima; M. Nakaya IEEE Journal of Solid-State Circuits, 1993

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single ...


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Educational Resources on Demultiplexing

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eLearning

Ultra-high-speed serial optical communications: Enabling technologies

L. K. Oxenlowe; M. Galili; H. C. H. Mulvad; H. Ji; A. T. Clausen; R. Kjaer; P. Jeppesen 2008 International Conference on Photonics in Switching, 2008

This paper will present recently identified and demonstrated key technologies for ultra-high-speed serial communications. Certain key components such as stabilised highly non-linear fibre switches, periodically poled Lithium Niobate devices and semiconductor optical amplifiers will be described with demonstrations of 640 Gb/s transmission, clock recovery, demultiplexing, add/drop, wavelength conversion and channel identification. Timing jitter tolerance is addressed through techniques to create ...


Highly nonlinear Chalcogenide waveguide devices for ultra-fast all-optical signal processing

M. D. Pelusi; F. Luan; E. C. Magi; M. R. E. Lamont; D. Moss; B. J. Eggleton; S. Madden; D. -Y. Choi; D. A. P. Bulla; B. Luther-Davies 2008 IEEE PhotonicsGlobal@Singapore, 2008

A review of the development and applications of compact highly nonlinear Chalcogenide waveguides for ultra-fast all-optical signal processing is presented. We demonstrate the extreme tapering of a highly nonlinear As2S3 fiber to further increase its nonlinearity by more than an order of magnitude thereby enabling time-division demultiplexing of a 160 Gb/s signal by four- wave mixing (FWM) with significantly lower ...


Low supply voltage operation of 40-Gb/s full-rate 4:1 multiplexer based on parallel-current-switching latch circuitry

Y. Amamiya; Y. Suzuki; Y. Yamazaki; M. Mamada; H. Hida IEEE Compound Semiconductor Integrated Circuit Symposium, 2004., 2004

We implemented new circuit topology, a parallel-current-switching latch, in a full-rate 4:1 multiplexer using InP-HBT technology. This is the first report of this technology, which resulted in 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. This voltage is as low as that of high-speed CMOS I/O circuits. This circuit topology ...


Design and Implementation of an MHP Video and Graphics Subsystem on Xilinx ML310 Platform

Min-hong Chen; Feng-cheng Chang; Hsueh-ming Hang 2006 International Conference on Intelligent Information Hiding and Multimedia, 2006

Multimedia Home Platform (MHP) is a standard to enable versatile applications of a DVB program. In this paper, we design and implement a simplified MHP video and graphics subsystem. The Xilinx ML310 is chosen as the hardware platform to implement our design. The execution environment consists of an embedded Linux, a frame-buffer based X server, and a Java ME Personal ...


A 622-Mb/s 8×8 ATM switch chip set with shared multibuffer architecture

H. Kondoh; H. Notani; H. Yamanaka; K. Higashitani; H. Saito; I. Hayashi; S. Kohama; Y. Matsuda; K. Oshima; M. Nakaya IEEE Journal of Solid-State Circuits, 1993

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single ...


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IEEE.tv Videos

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IEEE-USA E-Books

  • A 10Gb/s CMOS Clock and Data Recovery Circuit with a HalfRate Linear Phase Detector

    A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-µm CMOS technology in an area of 1.1 x 0.9 mm2, the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28 x 10-6, with random data input of length 223 - 1. The power dissipation is 72 mW from a 2.5-V supply.

  • A Monolithic 480 Mb/s Parallel AGC/Decision/ClockRecovery Circuit in 1.2m CMOS

    A parallel architecture for high-data-rate AGC/decision/clock-recovery circuit, recovering digital NRZ data in optical-fiber receivers, is described. Improvement over traditional architecture in throughput is achieved through the use of parallel signal paths. An experimental prototype, fabricated in a 1.2-µm double-poly double-metal n-well CMOS process, achieves a maximum bit rate of 480 Mb/s. The chip contains variable gain amplifiers, clock recovery, and demultiplexing circuits. It yields a HER of 10- 11 with an 18 mV p-p differential input signal. The power consumption is 900 mW from a single 5 V supply.



Standards related to Demultiplexing

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