720 resources related to DRAM chips
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Topics of interest include, but are not limited to:+Processor, cache, and memory architectures+Parallel computer architectures+Multicore architectures+Impact of technology on architecture+Power-efficient architectures and techniques+Dependable/secure architectures+High-performance I/O systems+Embedded and reconfigurable architectures+Interconnect and network interface architectures+Architectures for cloud-based HPC and data centers+Innovative hardware/software trade-offs+Impact of compilers and system software on architecture+Performance modeling and evaluation+Architectures for emerging technology and applications
2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2013 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc.
2013 IEEE International 3D Systems Integration Conference (3DIC)
Technologies for enabling 3D systems based on Through Silicon Vias.
IEEE EUROCON 2013
The IEEE Region 8 EuroCon 2013 Conference is a premier forum for the exchange of ideas, open and direct discussion on the development of the Circuits and Systems, Multimedia, Information and Communication Technology and energy and power systems. It has achieved a considerable success during the past seven editions covering majority of the fields in the area of electrical engineering.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
The goal of IEEE Transactions on Multimedia is to integrate all aspects of multimedia systems and technology, signal processing, and applications. It will cover various aspects of research in multimedia technology and applications including, but not limited to: circuits, algorithms and macro/micro-architectures, software, detailed design, synchronization, interaction, joint processing and coordination of multimedia and multimodal signals/data, compression, storage, retrieval, communication, ...
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...
Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.
Miyamoto, Kazutoshi; Nakagawa, Osamu; Mitsuhashi, Junichi; Matsumoto, Heihachi Reliability Physics Symposium, 1986. 24th Annual, 1986
The effect of long-term high temperature stress on the filler-induced failure in high density MOS RAMs was investigated. High temperature storage causes volume reduction in some plastic resins which enhances the local strong stress to RAM chip resulting in the filler-induced failure. This phenonenon is well explained by the increase of leakage current in p-n junction under local strong stress.
Brent, Richard P. Frontiers of Massively Parallel Computation, 1992., Fourth Symposium on the, 1992
The author describes an implementation of the LINPACK benchmark on the Fujitsu AP 1000. Design considerations include communication primitives, data distribution, use of blocking to reduce memory references, and effective use of the cache. The LINPACK benchmark results show that the AP 1000 is a good machine for numerical linear algebra, and that one can consistently achieve close to 80 ...
Dong-Il Moon; Jee-Yeon Kim; Hyunjae Jang; Hee-Jeong Hong; Choong Ki Kim; Jae-Sub Oh; Min-Ho Kang; Jeoung-Woo Kim; Yang-Kyu Choi Electron Device Letters, IEEE, 2014
A trigate FinFET with a charge trap gate dielectric is demonstrated for high- speed and long retention memory applications. For a capacitor-less dynamic memory cell, a nitride layer is utilized as a charge storage node and it is directly formed on a silicon channel. In addition, novel gate-stacks allow high-speed and write processes under low voltage WITH remarkably endurable operation ...
Kim, C.H.; Chang, L. Design & Test of Computers, IEEE, 2011
This special issue presents seven articles that examine the characteristics, capabilities, and challenges of various embedded memories, especially those designed in emerging technologies. The articles address the intricacies and trade-offs required by designers when faced with scaling and power constraints.
Ho Young Song; Seong Jin Jang; Jin Seok Kwak; Cheol Su Kim; Chang Man Kang; Dae Hyun Jeong; Yun Sik Park; Min Sang Park; Kyoung Su Byun; Woo Jin Lee; Young Cheol Cho; Won Hwa Shin; Young Uk Jang; Seok Won Hwang; Young Hyun Jun; Soo In Cho Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, 2003
For operating frequencies exceeding 500 MHz, the timing margin of the I/O interface is critical and requires the data input-output timing accuracy to be within 200 ps. To meet the requirement, the designed SDRAM adopts a digitally self-calibrated on-die-termination with linearity error of /spl plusmn/1% and achieves over 1.2 Gbps/pin stable operation by using window matching and latency control. The ...
Ellis, Wayne Effects of Reliability Mechanisms On VLSI Circuit Functionality, 2004
This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to ...
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