725 resources related to DRAM chips
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Topics of interest include, but are not limited to:+Processor, cache, and memory architectures+Parallel computer architectures+Multicore architectures+Impact of technology on architecture+Power-efficient architectures and techniques+Dependable/secure architectures+High-performance I/O systems+Embedded and reconfigurable architectures+Interconnect and network interface architectures+Architectures for cloud-based HPC and data centers+Innovative hardware/software trade-offs+Impact of compilers and system software on architecture+Performance modeling and evaluation+Architectures for emerging technology and applications
2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2013 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc.
2013 IEEE International 3D Systems Integration Conference (3DIC)
Technologies for enabling 3D systems based on Through Silicon Vias.
IEEE EUROCON 2013
The IEEE Region 8 EuroCon 2013 Conference is a premier forum for the exchange of ideas, open and direct discussion on the development of the Circuits and Systems, Multimedia, Information and Communication Technology and energy and power systems. It has achieved a considerable success during the past seven editions covering majority of the fields in the area of electrical engineering.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
The goal of IEEE Transactions on Multimedia is to integrate all aspects of multimedia systems and technology, signal processing, and applications. It will cover various aspects of research in multimedia technology and applications including, but not limited to: circuits, algorithms and macro/micro-architectures, software, detailed design, synchronization, interaction, joint processing and coordination of multimedia and multimodal signals/data, compression, storage, retrieval, communication, ...
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...
Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.
Scheuerlein, R.E.; Walker, W.W.; Morency, D.G.; Noble, W.P.; Bakeman, P.E.; Critchlow, D.L. Solid-State Circuits, IEEE Journal of, 1984
A novel memory cell which has a 2-to-1 cell packaging density advantage relative to a conventional one-device (1D) dynamic RAM cell is described. In the shared word line (SWL) DRAM cell, a pair of cells is connected to the same bit sense line and word line. Unique read and write operations are accomplished by controlling the plate of the storage ...
Vander Wiel, S.P.; Lilja, D.J. Computer, 1997
With data prefetching, memory systems call data into the cache before the processor needs it, thereby reducing memory-access latency. Using the most suitable techniques is critical to maximizing data prefetching's effectiveness. The authors review three popular prefetching techniques: software-initiated prefetching, sequential hardware-initiated prefetching, and prefetching via reference prediction tables
Takai, Y.; Nagase, M.; Kitamura, M.; Koshikawa, Y.; Yoshida, N.; Kobayashi, Y.; Obara, T.; Fukuzo, Y.; Watanabe, H. VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on, 1993
A 3.3 V 512 k/spl times/18/spl times/2 bank synchronous DRAM has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means, is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in ...
Kurosawa, T. COMPCON Fall '77, 1977
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Chan, J.Y.; Barnes, J.J.; Wang, C.Y.; De Blasi, J.M.; Guidry, M.R. Solid-State Circuits, IEEE Journal of, 1980
A new high performance 36500 mil/SUP 2/ 64K dynamic RAM has been designed and incorporates: 1) a twisted-metal bit-line architecture, 2) an ultrasensitive sense amplifier with self-restore to V/SUB DD/, 3) internal constant-voltage supply to memory cell plate, 4) a bit-line equalizer and full-size reference capacitor, 5) high-performance enhancement-depletion mode inverter-buffer circuits, 6) TTL negative undershoot protection on address circuits, ...
Ellis, Wayne Effects of Reliability Mechanisms On VLSI Circuit Functionality, 2004
This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to ...
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