730 resources related to DRAM chips
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Topics of interest include, but are not limited to:+Processor, cache, and memory architectures+Parallel computer architectures+Multicore architectures+Impact of technology on architecture+Power-efficient architectures and techniques+Dependable/secure architectures+High-performance I/O systems+Embedded and reconfigurable architectures+Interconnect and network interface architectures+Architectures for cloud-based HPC and data centers+Innovative hardware/software trade-offs+Impact of compilers and system software on architecture+Performance modeling and evaluation+Architectures for emerging technology and applications
2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2013 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc.
2013 IEEE International 3D Systems Integration Conference (3DIC)
Technologies for enabling 3D systems based on Through Silicon Vias.
IEEE EUROCON 2013
The IEEE Region 8 EuroCon 2013 Conference is a premier forum for the exchange of ideas, open and direct discussion on the development of the Circuits and Systems, Multimedia, Information and Communication Technology and energy and power systems. It has achieved a considerable success during the past seven editions covering majority of the fields in the area of electrical engineering.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
The goal of IEEE Transactions on Multimedia is to integrate all aspects of multimedia systems and technology, signal processing, and applications. It will cover various aspects of research in multimedia technology and applications including, but not limited to: circuits, algorithms and macro/micro-architectures, software, detailed design, synchronization, interaction, joint processing and coordination of multimedia and multimodal signals/data, compression, storage, retrieval, communication, ...
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...
Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.
Vander Wiel, S.P.; Lilja, D.J. Computer, 1997
With data prefetching, memory systems call data into the cache before the processor needs it, thereby reducing memory-access latency. Using the most suitable techniques is critical to maximizing data prefetching's effectiveness. The authors review three popular prefetching techniques: software-initiated prefetching, sequential hardware-initiated prefetching, and prefetching via reference prediction tables
Meaney, P.J.; Lastras-Montano, L.A.; Papazova, V.K.; Stephens, E.; Johnson, J.S.; Alves, L.C.; O'Connor, J.A.; Clarke, W.J. IBM Journal of Research and Development, 2012
The IBM zEnterprise® system introduced a new and innovative redundant array of independent memory (RAIM) subsystem design as a standard feature on all zEnterprise servers. It protects the server from single-channel errors such as sudden control, bus, buffer, and massive dynamic RAM (DRAM) failures, thus achieving the highest System z® memory availability. This system also introduced innovations such as DRAM ...
Knudson, A.R.; Campbell, A.B. Nuclear Science, IEEE Transactions on, 1983
The charge from electron-hole pairs, produced by the passage of a charged particle, may be sufficiently large to alter the stored information in modern dynamic random access memories (dRAMs), thus producing a soft upset. A microbeam from a 5-MV Van de Graaff has been used to investigate the upset process in 64K dRAMs. The microbeam has also been used to ...
Rodgers, T.; Jenne, F.; Frederick, B.; Barnes, J.; Hiltpold, W.; Trotter, J. Solid-State Circuits Conference. Digest of Technical Papers. 1977 IEEE International, 1977
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Striny, Kurt M.; Schelling, A. Components, Hybrids, and Manufacturing Technology, IEEE Transactions on, 1981
Analysis of accelerated aging data indicates that room temperature vulcanizing (RTV) silicone rubber coated aluminum metallized N-type metal-oxide semiconductor (NMOS) devices in plastic packages will perform reliably in typical Bell System use environments. For example, a 4K bit dynamic random access memory (DRAM) operating with zero power dissipation in a worst case central office environment will reach 100 FIT1failure rate ...
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