DRAM chips
4,480 resources related to DRAM chips
Conferences related to DRAM chips
Back to Top2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)
Visit websiteThe world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments\, keynotes\, panels\, plus User Track presentations. A diverse worldwide community representing more than 1\,000 organization attends each year\, from system designers and architects\, logic and circuit designers\, validation engineers\, CAD managers\, senior managers and executives to researchers and academicians from leading universities.
2012 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS)
Visit websitePerformance and Power Analysis of Computer Systems and Software.
2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA)
Visit websiteProcessor, cache, memory, parallel, multicore, multiprocessor, power-efficient, reliable, secure, embedded, reconfigurable, heterogehous, network processor, interconnect and network interface, emerging, and/or high-performance architectures, Impact of technology on architecture, High-performance I/O systems, Hardware/software trade-offs, Impact of compilers and system software on architecture, Performance modeling, simulation, and projection techniques, applications.
IEEE EUROCON 2011 - International Conference on Computer as a Tool (EUROCON)
Visit websiteMain topics: Telecommunications and Multimedia Systems; Information Technologies and Intelligent Systems; CIRCUITS AND SYSTEMS; POWER SYSTEMS AND RENEWABLE RESOURCES; EDUCATION; ENGINEERING MANAGEMENT To promote interaction between industry and academia contributions of recent industrial developments will be accepted and published in a maximum 1-page of abstract and 1-page of figures.
2010 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Visit websiteApplication-specific systems: network computing, special-purpose systems, performance evaluation, design languages, compilers, operating systems, nanocomputing systems and applications, hardware/software integration and rapid prototyping. Application-specific architectures: special-purpose designs, design methodology, CAD tools, fault tolerance, specifications and interfaces, networks-on-a-chip, hardware/software co-design, processor arrays, SoC, superscalar, multithreaded, VLIW and EPIC architectures.
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Xplore Articles related to DRAM chips
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Exploration and Optimization of 3-D Integrated DRAM Subsystems
Weis, C.; Loi, I.; Benini, L.; Wehn, N. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2013
Energy efficiency is the major optimization criterion for systems-on-chip (SoCs) for mobile devices (smartphones and tablets). Through silicon via (TSV) technology enables 3-D integration of dies and the heterogeneous stacking of multiple memory or logic layers, allowing increased bandwidth and lower energy consumption of the memory interface compared to traditional approaches. In this paper, we explore the 3-D-DRAM architecture design ...
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Hardware/software techniques for DRAM thermal management
Song Liu; Leung, B.; Neckar, A.; Memik, S.O.; Memik, G.; Hardavellas, N. High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, 2011
The performance of the main memory is an important factor on overall system performance. To improve DRAM performance, designers have been increasing chip densities and the number of memory modules. However, these approaches increase power consumption and operating temperatures: temperatures in existing DRAM modules can rise to over 95°C. Another important property of DRAM temperature is the large variation in ...
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CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory
Ke Chen; Sheng Li; Muralimanohar, N.; Ahn, Jung Ho; Brockman, J.B.; Jouppi, N.P. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, 2012
Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future memory architectures to satisfy the ever-increasing demands on performance, power, and cost. This paper introduces CACTI-3DD, the first architecture-level integrated power, area, and timing modeling framework for 3D die-stacked off-chip DRAM main memory. CACTI-3DD includes TSV models, improves models for 2D off-chip DRAM main memory over ...
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Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
Dong Hyuk Woo; Nak Hee Seong; Lee, H.-H.S. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2013
As scaling DRAM cells becomes more challenging and energy-efficient DRAM chips are in high demand, the DRAM industry has started to undertake an alternative approach to address these looming issues-that is, to vertically stack DRAM dies with through-silicon-vias (TSVs) using 3-D-IC technology. Furthermore, this emerging integration technology also makes heterogeneous die stacking in one DRAM package possible. Such a heterogeneous ...
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A study of DRAM failures in the field
Sridharan, V.; Liberty, D. High Performance Computing, Networking, Storage and Analysis (SC), 2012 International Conference for, 2012
Most modern computer systems use dynamic random access memory (DRAM) as a main memory store. Recent publications have confirmed that DRAM errors are a common source of failures in the field. Therefore, further attention to the faults experienced by DRAM sub-systems is warranted. In this paper, we present a study of 11 months of DRAM errors in a large high-performance ...
Jobs related to DRAM chips
Back to TopHardware Test & Design Engineer - Probe Card Design and Development Qualcomm, Inc.
Memory Architect Qualcomm, Inc.
High-Speed DDR PHY Designer - All Levels Qualcomm, Inc.
Hardware Characterization Engineer Qualcomm, Inc.
DDR and Cache System Micro-architect Qualcomm, Inc.
RF / Analog Verification Engineer Qualcomm, Inc.
High Speed IO Design Engineer - Raleigh, NC (RTP) Qualcomm, Inc.
Embedded Software Applications Engineer - Windows Drivers (Redmond, WA) Qualcomm, Inc.
Embedded Software Applications Engineer - Windows Drivers (San Diego CA) Qualcomm, Inc.
ASIC Design & Implementation Specialist Qualcomm, Inc.
Senior Verification Engineer Qualcomm, Inc.
Senior Physical Design Engineer Qualcomm, Inc.
Senior Physical Design Engineer Qualcomm, Inc.
Graphics Driver Software Engineer Qualcomm, Inc.
Graphics Driver Software Engineer Qualcomm, Inc.
Graphics Driver Software Engineer (New Grads Welcome) Qualcomm, Inc.
Graphics Driver Software Engineer, Senior & Staff Qualcomm, Inc.
Graphics Software Engineer Qualcomm, Inc.
Quality Assurance & Testing Engineer -- Consumer Electronics (consumer product testing and eval) Company Confidential
Chipset Architect Qualcomm, Inc.
SOC Architect Qualcomm, Inc.
Digital Verification Lead - (San Diego, CA) Qualcomm, Inc.
ASIC Digital Designer Qualcomm, Inc.
Physical Verification Specialist Qualcomm, Inc.
Educational Resources on DRAM chips
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Effects of Reliability Mechanisms On VLSI Circuit Functionality
Ellis, Wayne Effects of Reliability Mechanisms On VLSI Circuit Functionality, 2004
This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to ...
Periodicals related to DRAM chips
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Solid-State Circuits, IEEE Journal of
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...
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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.
IEEE Organizations related to DRAM chips
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- Council on Electronic Design Automation
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