41 resources related to DRAM chips
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
All aspects of high-performance computer architecture: Processor, cache, memory architectures; Multicore, parallel architectures; Embedded, reconfigurable, dependable/secure architectures; Impact of compilers and system software on architecture; Performance modeling and evaluation; High-performance I/O systems; Architectures for cloud-based HPC; Interconnect and network interface architectures; Innovative hardware/software trade-offs.
2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2013 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc.
2013 IEEE International 3D Systems Integration Conference (3DIC)
Technologies for enabling 3D systems based on Through Silicon Vias.
The IEEE International Symposium on Performance Analysis of Systems and Software provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software.
Weis, C.; Loi, I.; Benini, L.; Wehn, N. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2013
Energy efficiency is the major optimization criterion for systems-on-chip (SoCs) for mobile devices (smartphones and tablets). Through silicon via (TSV) technology enables 3-D integration of dies and the heterogeneous stacking of multiple memory or logic layers, allowing increased bandwidth and lower energy consumption of the memory interface compared to traditional approaches. In this paper, we explore the 3-D-DRAM architecture design ...
Song Liu; Leung, B.; Neckar, A.; Memik, S.O.; Memik, G.; Hardavellas, N. High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, 2011
The performance of the main memory is an important factor on overall system performance. To improve DRAM performance, designers have been increasing chip densities and the number of memory modules. However, these approaches increase power consumption and operating temperatures: temperatures in existing DRAM modules can rise to over 95°C. Another important property of DRAM temperature is the large variation in ...
Dong Hyuk Woo; Nak Hee Seong; Lee, H.-H.S. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2013
As scaling DRAM cells becomes more challenging and energy-efficient DRAM chips are in high demand, the DRAM industry has started to undertake an alternative approach to address these looming issues-that is, to vertically stack DRAM dies with through-silicon-vias (TSVs) using 3-D-IC technology. Furthermore, this emerging integration technology also makes heterogeneous die stacking in one DRAM package possible. Such a heterogeneous ...
Sridharan, V.; Liberty, D. High Performance Computing, Networking, Storage and Analysis (SC), 2012 International Conference for, 2012
Most modern computer systems use dynamic random access memory (DRAM) as a main memory store. Recent publications have confirmed that DRAM errors are a common source of failures in the field. Therefore, further attention to the faults experienced by DRAM sub-systems is warranted. In this paper, we present a study of 11 months of DRAM errors in a large high-performance ...
Ke Chen; Sheng Li; Muralimanohar, N.; Ahn, Jung Ho; Brockman, J.B.; Jouppi, N.P. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, 2012
Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future memory architectures to satisfy the ever-increasing demands on performance, power, and cost. This paper introduces CACTI-3DD, the first architecture-level integrated power, area, and timing modeling framework for 3D die-stacked off-chip DRAM main memory. CACTI-3DD includes TSV models, improves models for 2D off-chip DRAM main memory over ...
No jobs are currently tagged "DRAM chips"
Ellis, Wayne Effects of Reliability Mechanisms On VLSI Circuit Functionality, 2004
This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to ...
No standards are currently tagged "DRAM chips"
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...
Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.