725 resources related to DRAM chips
- Topics related to DRAM chips
- IEEE Organizations related to DRAM chips
- Conferences related to DRAM chips
- Periodicals related to DRAM chips
- Most published Xplore authors for DRAM chips
The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Topics of interest include, but are not limited to:+Processor, cache, and memory architectures+Parallel computer architectures+Multicore architectures+Impact of technology on architecture+Power-efficient architectures and techniques+Dependable/secure architectures+High-performance I/O systems+Embedded and reconfigurable architectures+Interconnect and network interface architectures+Architectures for cloud-based HPC and data centers+Innovative hardware/software trade-offs+Impact of compilers and system software on architecture+Performance modeling and evaluation+Architectures for emerging technology and applications
2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2013 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc.
2013 IEEE International 3D Systems Integration Conference (3DIC)
Technologies for enabling 3D systems based on Through Silicon Vias.
IEEE EUROCON 2013
The IEEE Region 8 EuroCon 2013 Conference is a premier forum for the exchange of ideas, open and direct discussion on the development of the Circuits and Systems, Multimedia, Information and Communication Technology and energy and power systems. It has achieved a considerable success during the past seven editions covering majority of the fields in the area of electrical engineering.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
The goal of IEEE Transactions on Multimedia is to integrate all aspects of multimedia systems and technology, signal processing, and applications. It will cover various aspects of research in multimedia technology and applications including, but not limited to: circuits, algorithms and macro/micro-architectures, software, detailed design, synchronization, interaction, joint processing and coordination of multimedia and multimodal signals/data, compression, storage, retrieval, communication, ...
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...
Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.
Eldin, A.G.; Elmasry, M. Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European, 1984
A high density dynamic memory cell using the CMOS technology (JCMOS cell) is described. The cell is based on merging three different devices and occupies an area of a single MOS transistor The cell consists of an enhancement surface MOSFET, a JFET and a bipolar transistor The data is stored on the MOS capacitor, sensed by the JFET and written ...
Ha, D.; Changhyun Cho; Shin, D.; Gwan-Hyeob Koh; Tae-Young Chung; Kim, Kinam Electron Devices, IEEE Transactions on, 1999
As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When ...
Brent, Richard P. Frontiers of Massively Parallel Computation, 1992., Fourth Symposium on the, 1992
The author describes an implementation of the LINPACK benchmark on the Fujitsu AP 1000. Design considerations include communication primitives, data distribution, use of blocking to reduce memory references, and effective use of the cache. The LINPACK benchmark results show that the AP 1000 is a good machine for numerical linear algebra, and that one can consistently achieve close to 80 ...
Chen, H.H. Emerging Information Technology Conference, 2005., 2005
This paper describes a hierarchical built-in self-test (BIST) method for testing an integrated system chip with a global BIST controller, multiple local BIST circuits for each macro, and data/control paths to perform the system-on-chip (SoC) test operations. The global BIST controller is composed of programmable devices for storing the test patterns and programming the test commands, a state machine for ...
Reese, E.A.; Spaderna, D.W.; Flannagan, S.T.; Tsang, F. Solid-State Circuits, IEEE Journal of, 1981
A 4K/spl times/8 MOS dynamic RAM using a single transistor cell with on-chip self-refresh is described. The device uses a multiplexed address/data bus. Control of the reconfigurable data bus allows the RAM to operate on either an 8-bit or a 16-bit data bus. The memory cell is fabricated using a double polysilicon n-channel HMOS technology using polysilicon word lines and ...
Ellis, Wayne Effects of Reliability Mechanisms On VLSI Circuit Functionality, 2004
This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to ...
No standards are currently tagged "DRAM chips"