Conferences related to DRAM chips

Back to Top

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers. Analog Circuits [x] Analog/mixed-signal [x] Design For Manufacturability [x] Design Verification [x] Embedded Systems [x] Emerging Design Technologies [x] Fpga [x] Green Technology [x] High-level Synthesis [x] Interconnect [x] Low-power Design [x] Physical Design [x] Reconfigurable Computing [x] Reliability [x] Rf Design [x] Synthesis [x] System-level Design [x] Testing And Verification [x]


2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

Topics of interest include, but are not limited to: +Processor, cache, and memory architectures +Parallel computer architectures +Multicore architectures +Impact of technology on architecture +Power-efficient architectures and techniques +Dependable/secure architectures +High-performance I/O systems +Embedded and reconfigurable architectures +Interconnect and network interface architectures +Architectures for cloud-based HPC and data centers +Innovative hardware/software trade-offs +Impact of compilers and

  • 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

    All aspects of high-performance computer architecture: Processor, cache, memory architectures; Multicore, parallel architectures; Embedded, reconfigurable, dependable/secure architectures; Impact of compilers and system software on architecture; Performance modeling and evaluation; High-performance I/O systems; Architectures for cloud-based HPC; Interconnect and network interface architectures; Innovative hardware/software trade-offs.

  • 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA)

    Processor, cache, memory, parallel, multicore, multiprocessor, power-efficient, reliable, secure, embedded, reconfigurable, heterogehous, network processor, interconnect and network interface, emerging, and/or high-performance architectures, Impact of technology on architecture, High-performance I/O systems, Hardware/software trade-offs, Impact of compilers and system software on architecture, Performance modeling, simulation, and projection techniques, applications.

  • 2010 IEEE 16th International Symposium on High Performance Computer Architecture (HPCA)

    The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to: Processor architectures, Cache and memory systems, Parallel computer architectures, Impact of technology on architecture, Power-efficient architectures and techni

  • 2009 IEEE 15th International Symposium on High Performance Computer Architecture (HPCA)

    The International Symposium on High-Performance Computer Architecture is a premier forum for scientists and engineers to present their latest research findings in all areas of computer architecture, including processor architecture, cache and memory system design, power-efficient designs, reliable architectures, secure architectures, high-performance I/O systems, embedded and reconfigurable architectures, interconnects and on-chip networks, the impact of compilers and operating systems on architecture, and performance modeling and evaluation.

  • 2008 IEEE 14th International Symposium on High Performance Computer Architecture (HPCA)

  • 2007 IEEE 13th International Symposium on High Performance Computer Architecture (HPCA)

  • 2006 IEEE 12th International Symposium on High Performance Computer Architecture (HPCA)

  • 2005 IEEE 11th International Symposium on High Performance Computer Architecture (HPCA)


2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)

The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2013 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc.

  • 2012 IEEE 23rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2012 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc. We especially encourage submissions in the following three areas: Bioinformatics and computational biology - life sciences present a host of interesting problems that can benefit from application-specifi

  • 2010 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    Application-specific systems: network computing, special-purpose systems, performance evaluation, design languages, compilers, operating systems, nanocomputing systems and applications, hardware/software integration and rapid prototyping. Application-specific architectures: special-purpose designs, design methodology, CAD tools, fault tolerance, specifications and interfaces, networks-on-a-chip, hardware/software co-design, processor arrays, SoC, superscalar, multithreaded, VLIW and EPIC architectures.

  • 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    The conference will cover the theory and practice of application-specific systems, architectures and processors. Areas for application-specific computing are many and varied. Some sample application areas include information systems, signal and image processing, multimedia systems, communication, high-speed networks, sensor networks, compression, graphics, cryptography, and many areas of computational science.


2013 IEEE International 3D Systems Integration Conference (3DIC)

Technologies for enabling 3D systems based on Through Silicon Vias.

  • 2011 IEEE International 3D Systems Integration Conference (3DIC)

    3DIC 2012 will cover all 3D Integration topics, including 3D process technology, materials, equipment, circuits technology, design and test methodology and applications. The conference invites authors and attendees to submit and interact with 3D integration researchers from all around the world.

  • 2010 IEEE International 3D Systems Integration Conference (3DIC)

    3DIC 2010 will cover all 3D Integration topics, including 3D process technology, materials, equipment, circuits technology, design methodology and applications.

  • 2009 3rd International Conference on 3D System Integration (3DIC)

    covers all the topics in 3DIC, including 3D process technology, materials, equipment, circuits technology, design methodology and applications.


IEEE EUROCON 2013

The IEEE Region 8 EuroCon 2013 Conference is a premier forum for the exchange of ideas, open and direct discussion on the development of the Circuits and Systems, Multimedia, Information and Communication Technology and energy and power systems. It has achieved a considerable success during the past seven editions covering majority of the fields in the area of electrical engineering.


More Conferences

Periodicals related to DRAM chips

Back to Top

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Multimedia, IEEE Transactions on

The goal of IEEE Transactions on Multimedia is to integrate all aspects of multimedia systems and technology, signal processing, and applications. It will cover various aspects of research in multimedia technology and applications including, but not limited to: circuits, algorithms and macro/micro-architectures, software, detailed design, synchronization, interaction, joint processing and coordination of multimedia and multimodal signals/data, compression, storage, retrieval, communication, ...


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.




Xplore Articles related to DRAM chips

Back to Top

Exploration and Optimization of 3-D Integrated DRAM Subsystems

Weis, C.; Loi, I.; Benini, L.; Wehn, N. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2013

Energy efficiency is the major optimization criterion for systems-on-chip (SoCs) for mobile devices (smartphones and tablets). Through silicon via (TSV) technology enables 3-D integration of dies and the heterogeneous stacking of multiple memory or logic layers, allowing increased bandwidth and lower energy consumption of the memory interface compared to traditional approaches. In this paper, we explore the 3-D-DRAM architecture design ...


Improving DRAM performance by parallelizing refreshes with accesses

Chang, K.K.-W.; Donghyuk Lee; Chishti, Z.; Alameldeen, A.R.; Wilkerson, C.; Yoongu Kim; Mutlu, O. High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on, 2014

Modern DRAM cells are periodically refreshed to prevent data loss due to leakage. Commodity DDR (double data rate) DRAM refreshes cells at the rank level. This degrades performance significantly because it prevents an entire DRAM rank from serving memory requests while being refreshed. DRAM designed for mobile platforms, LPDDR (low power DDR) DRAM, supports an enhanced mode, called per-bank refresh, ...


Tiered-latency DRAM: A low latency and low cost DRAM architecture

Donghyuk Lee; Yoongu Kim; Seshadri, V.; Liu, J.; Subramanian, L.; Mutlu, O. High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on, 2013

The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of increasingly large and complex computer systems. However, DRAM latency has remained almost constant, making memory latency the performance bottleneck in today's systems. We observe that the high access latency is not intrinsic to DRAM, but a trade-off made to decrease cost-per-bit. To mitigate the high area ...


Hardware/software techniques for DRAM thermal management

Song Liu; Leung, B.; Neckar, A.; Memik, S.O.; Memik, G.; Hardavellas, N. High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, 2011

The performance of the main memory is an important factor on overall system performance. To improve DRAM performance, designers have been increasing chip densities and the number of memory modules. However, these approaches increase power consumption and operating temperatures: temperatures in existing DRAM modules can rise to over 95°C. Another important property of DRAM temperature is the large variation in ...


Skinflint DRAM system: Minimizing DRAM chip writes for low power

Yebin Lee; Soontae Kim; Seokin Hong; Jongmin Lee High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on, 2013

DRAMs are one of the main players of computer system energy consumption due to their large capacities and frequent accesses. Consequently, many schemes have been proposed to reduce DRAM power/energy consumption. Some of them propose new DRAM system and chip organizations, which are effective in reducing power consumption but intrusive. In contrast, we minimize DRAM write accesses at chip level ...


More Xplore Articles

Educational Resources on DRAM chips

Back to Top

eLearning

Effects of Reliability Mechanisms On VLSI Circuit Functionality

Ellis, Wayne Effects of Reliability Mechanisms On VLSI Circuit Functionality, 2004

This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to ...


IEEE-USA E-Books

No IEEE-USA E-Books are currently tagged "DRAM chips"



Standards related to DRAM chips

Back to Top

No standards are currently tagged "DRAM chips"


Jobs related to DRAM chips

Back to Top

No jobs are currently tagged "DRAM chips"