729 resources related to DRAM chips
- Topics related to DRAM chips
- IEEE Organizations related to DRAM chips
- Conferences related to DRAM chips
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Topics of interest include, but are not limited to:+Processor, cache, and memory architectures+Parallel computer architectures+Multicore architectures+Impact of technology on architecture+Power-efficient architectures and techniques+Dependable/secure architectures+High-performance I/O systems+Embedded and reconfigurable architectures+Interconnect and network interface architectures+Architectures for cloud-based HPC and data centers+Innovative hardware/software trade-offs+Impact of compilers and system software on architecture+Performance modeling and evaluation+Architectures for emerging technology and applications
2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2013 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc.
2013 IEEE International 3D Systems Integration Conference (3DIC)
Technologies for enabling 3D systems based on Through Silicon Vias.
IEEE EUROCON 2013
The IEEE Region 8 EuroCon 2013 Conference is a premier forum for the exchange of ideas, open and direct discussion on the development of the Circuits and Systems, Multimedia, Information and Communication Technology and energy and power systems. It has achieved a considerable success during the past seven editions covering majority of the fields in the area of electrical engineering.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
The goal of IEEE Transactions on Multimedia is to integrate all aspects of multimedia systems and technology, signal processing, and applications. It will cover various aspects of research in multimedia technology and applications including, but not limited to: circuits, algorithms and macro/micro-architectures, software, detailed design, synchronization, interaction, joint processing and coordination of multimedia and multimodal signals/data, compression, storage, retrieval, communication, ...
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...
Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.
Tanaka, T.; Ishiuchi, H.; Takeuchi, Y.; Ishikawa, M.; Mochizuki, T.; Ozawa, O. Electron Devices Meeting, 1981 International, 1981
MoSi2-gate buried channel MOSFETs as a transfer gate of a memory cell and an element of peripheral circuits of a 256k-bit dynamic RAM have been investigated. Two-dimensional numerical analysis predicts that MoSi2-gate buried channel MOSFETs have inherently larger subthreshold leakage current than conventional Si-gate MOSFETs, but it can be improved by a deep ion- implantation. Experimental results which support the ...
Yamada, K.; Yamabe, K.; Tsunashima, Y.; Imai, K.; Kashio, T.; Tango, H. Electron Devices Meeting, 1985 International, 1985
A deep-trenched capacitor technology is one of key processes for realizing 4Mb DRAM(1). Major subjects in this technology are to form a precisely controlled shallow diffusion layer at vertical side walls and to grow high reliable thin gate oxide on the trenched Si surface. In this paper, arsenic doping from As doped SiO2(AsSG) film into the vertical side walls and ...
Vander Wiel, S.P.; Lilja, D.J. Computer, 1997
With data prefetching, memory systems call data into the cache before the processor needs it, thereby reducing memory-access latency. Using the most suitable techniques is critical to maximizing data prefetching's effectiveness. The authors review three popular prefetching techniques: software-initiated prefetching, sequential hardware-initiated prefetching, and prefetching via reference prediction tables
Donchev, B.; Kuzmanov, G.; Gaydadjiev, G.N. System-on-Chip, 2006. International Symposium on, 2006
An implementation of an on chip memory (OCM) based dual data rate external memory controller (OCM2DDR) for Virtex II Pro is described. The proposed OCM2DDR controller comprises data side OCM (DSOCM) bus interface module, read and write control logic, halt read module and Xilinx DDR controller IP core. The presented design supports 16MB of external DDR memory and 32 to ...
Sai-Halasz, G. Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International, 1982
Monte Carlo procedures have been developed to obtain soft error rates (SER). The SER for a 1μm groundrule DRAM, due to alphas enamating from processing materials, shows the prevalence of multiple errors. SER reducing methods, using epi-layers, buried implant layers and Hi-C structures have been evaluated and found to be marginally effective.
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