Conferences related to DRAM chips

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2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.


2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

Topics of interest include, but are not limited to:+Processor, cache, and memory architectures+Parallel computer architectures+Multicore architectures+Impact of technology on architecture+Power-efficient architectures and techniques+Dependable/secure architectures+High-performance I/O systems+Embedded and reconfigurable architectures+Interconnect and network interface architectures+Architectures for cloud-based HPC and data centers+Innovative hardware/software trade-offs+Impact of compilers and system software on architecture+Performance modeling and evaluation+Architectures for emerging technology and applications


2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)

The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2013 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc.

  • 2012 IEEE 23rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2012 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc. We especially encourage submissions in the following three areas: Bioinformatics and computational biology - life sciences present a host of interesting problems that can benefit from application-specific solutions. Computational finance - the financial community has significant needs for high performance computing. Architecturally diverse systems - systems that use varied computing resources such as FPGAs, GPUs, Cell processors, etc.

  • 2010 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    Application-specific systems: network computing, special-purpose systems, performance evaluation, design languages, compilers, operating systems, nanocomputing systems and applications, hardware/software integration and rapid prototyping. Application-specific architectures: special-purpose designs, design methodology, CAD tools, fault tolerance, specifications and interfaces, networks-on-a-chip, hardware/software co-design, processor arrays, SoC, superscalar, multithreaded, VLIW and EPIC architectures.

  • 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    The conference will cover the theory and practice of application-specific systems, architectures and processors. Areas for application-specific computing are many and varied. Some sample application areas include information systems, signal and image processing, multimedia systems, communication, high-speed networks, sensor networks, compression, graphics, cryptography, and many areas of computational science.


2013 IEEE International 3D Systems Integration Conference (3DIC)

Technologies for enabling 3D systems based on Through Silicon Vias.

  • 2011 IEEE International 3D Systems Integration Conference (3DIC)

    3DIC 2012 will cover all 3D Integration topics, including 3D process technology, materials, equipment, circuits technology, design and test methodology and applications. The conference invites authors and attendees to submit and interact with 3D integration researchers from all around the world.

  • 2010 IEEE International 3D Systems Integration Conference (3DIC)

    3DIC 2010 will cover all 3D Integration topics, including 3D process technology, materials, equipment, circuits technology, design methodology and applications.

  • 2009 3rd International Conference on 3D System Integration (3DIC)

    covers all the topics in 3DIC, including 3D process technology, materials, equipment, circuits technology, design methodology and applications.


IEEE EUROCON 2013

The IEEE Region 8 EuroCon 2013 Conference is a premier forum for the exchange of ideas, open and direct discussion on the development of the Circuits and Systems, Multimedia, Information and Communication Technology and energy and power systems. It has achieved a considerable success during the past seven editions covering majority of the fields in the area of electrical engineering.


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Periodicals related to DRAM chips

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Multimedia, IEEE Transactions on

The goal of IEEE Transactions on Multimedia is to integrate all aspects of multimedia systems and technology, signal processing, and applications. It will cover various aspects of research in multimedia technology and applications including, but not limited to: circuits, algorithms and macro/micro-architectures, software, detailed design, synchronization, interaction, joint processing and coordination of multimedia and multimodal signals/data, compression, storage, retrieval, communication, ...


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.




Xplore Articles related to DRAM chips

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HeRMES: high-performance reliable MRAM-enabled storage

Miller, E.L.; Brandt, S.A.; Long, D.D.E. Hot Topics in Operating Systems, 2001. Proceedings of the Eighth Workshop on, 2001

Magnetic RAM (MRAM) is a new memory technology with access and cost characteristics comparable to those of conventional dynamic RAM (DRAM) and the non-volatility of magnetic media such as disk. Simply replacing DRAM with MRAM will make main memory non-volatile, but it will not improve file system performance. However, effective use of MRAM in a file system has the potential ...


Packaging process induced retention degradation of 256 Mbit DRAM with negative wordline bias

Minchen Chang; Jengping Lin; Ruey Dar Chang; Shih, S.N.; Chao-Sung Lai; Pei-Ing Lee Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the, 2004

The data retention time performance of 256 Mbit DRAM is degraded even in a 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and ...


A Study of Leveraging Memory Level Parallelism for DRAM System on Multi-core/Many-Core Architecture

Licheng Chen; Yongbing Huang; Yungang Bao; Guangming Tan; Zehan Cui; Mingyu Chen Trust, Security and Privacy in Computing and Communications (TrustCom), 2013 12th IEEE International Conference on, 2013

DRAM system has been more and more critical on modern multi-core/many-core architecture where the Moore's law has been made effect on increasing the number of cores integrated in a processor chip. The performance of DRAM system is usually measured in term of bandwidth and latency, which are regarded as inherently depending on Row Buffer Hit Rate (RBHR) according to previous ...


An 8 mm/sup 2/, 5 V 16K dynamic RAM using a new memory cell"

Meusburger, G.; Horninger, K.; Lindert, G. Solid-State Circuits, IEEE Journal of, 1978

A small 16K dynamic RAM utilizing a new memory cell configuration is described. The new cell has two selector transistors and makes a very short bit line possible. The memory on 8 mm/SUP 2/ is built in a scaled double polysilicon technology with 3.5 /spl mu/m line width. First samples achieved an access time of 160 ns.


A 72 K CMOS channellers gate array with embedded 1 Mbit dynamic RAM

Sawada, K.; Sakurai, T.; Nogami, K.; Iizuka, T.; Uchino, Y.; Tanaka, Y.; Kobayashi, T.; Kawagai, K.; Uchino, Y.; Tanaka, Y.; Kobayashi, T.; Kawagai, K.; Ban, E.; Shiotari, Y.; Itabashi, Y.; Kohyama, Susumu Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988, 1988

A 1-Mb DRAM (dynamic random-access memory) is embedded in a 72-K-raw-gates channelless gate array fabricated in 1.0-μm HC2 MOS twin-well technology. The DRAM design is optimized for embedding, such as the adaptation of no substrated bias design and p-well protected n-channel memory cells. The typical delay time of the gate array is 0.4 ns, and the worst-case access time of ...


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Educational Resources on DRAM chips

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eLearning

HeRMES: high-performance reliable MRAM-enabled storage

Miller, E.L.; Brandt, S.A.; Long, D.D.E. Hot Topics in Operating Systems, 2001. Proceedings of the Eighth Workshop on, 2001

Magnetic RAM (MRAM) is a new memory technology with access and cost characteristics comparable to those of conventional dynamic RAM (DRAM) and the non-volatility of magnetic media such as disk. Simply replacing DRAM with MRAM will make main memory non-volatile, but it will not improve file system performance. However, effective use of MRAM in a file system has the potential ...


Packaging process induced retention degradation of 256 Mbit DRAM with negative wordline bias

Minchen Chang; Jengping Lin; Ruey Dar Chang; Shih, S.N.; Chao-Sung Lai; Pei-Ing Lee Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the, 2004

The data retention time performance of 256 Mbit DRAM is degraded even in a 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and ...


A Study of Leveraging Memory Level Parallelism for DRAM System on Multi-core/Many-Core Architecture

Licheng Chen; Yongbing Huang; Yungang Bao; Guangming Tan; Zehan Cui; Mingyu Chen Trust, Security and Privacy in Computing and Communications (TrustCom), 2013 12th IEEE International Conference on, 2013

DRAM system has been more and more critical on modern multi-core/many-core architecture where the Moore's law has been made effect on increasing the number of cores integrated in a processor chip. The performance of DRAM system is usually measured in term of bandwidth and latency, which are regarded as inherently depending on Row Buffer Hit Rate (RBHR) according to previous ...


An 8 mm/sup 2/, 5 V 16K dynamic RAM using a new memory cell"

Meusburger, G.; Horninger, K.; Lindert, G. Solid-State Circuits, IEEE Journal of, 1978

A small 16K dynamic RAM utilizing a new memory cell configuration is described. The new cell has two selector transistors and makes a very short bit line possible. The memory on 8 mm/SUP 2/ is built in a scaled double polysilicon technology with 3.5 /spl mu/m line width. First samples achieved an access time of 160 ns.


A 72 K CMOS channellers gate array with embedded 1 Mbit dynamic RAM

Sawada, K.; Sakurai, T.; Nogami, K.; Iizuka, T.; Uchino, Y.; Tanaka, Y.; Kobayashi, T.; Kawagai, K.; Uchino, Y.; Tanaka, Y.; Kobayashi, T.; Kawagai, K.; Ban, E.; Shiotari, Y.; Itabashi, Y.; Kohyama, Susumu Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988, 1988

A 1-Mb DRAM (dynamic random-access memory) is embedded in a 72-K-raw-gates channelless gate array fabricated in 1.0-μm HC2 MOS twin-well technology. The DRAM design is optimized for embedding, such as the adaptation of no substrated bias design and p-well protected n-channel memory cells. The typical delay time of the gate array is 0.4 ns, and the worst-case access time of ...


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