723 resources related to DRAM chips
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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Topics of interest include, but are not limited to:+Processor, cache, and memory architectures+Parallel computer architectures+Multicore architectures+Impact of technology on architecture+Power-efficient architectures and techniques+Dependable/secure architectures+High-performance I/O systems+Embedded and reconfigurable architectures+Interconnect and network interface architectures+Architectures for cloud-based HPC and data centers+Innovative hardware/software trade-offs+Impact of compilers and system software on architecture+Performance modeling and evaluation+Architectures for emerging technology and applications
2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2013 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc.
2013 IEEE International 3D Systems Integration Conference (3DIC)
Technologies for enabling 3D systems based on Through Silicon Vias.
IEEE EUROCON 2013
The IEEE Region 8 EuroCon 2013 Conference is a premier forum for the exchange of ideas, open and direct discussion on the development of the Circuits and Systems, Multimedia, Information and Communication Technology and energy and power systems. It has achieved a considerable success during the past seven editions covering majority of the fields in the area of electrical engineering.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
The goal of IEEE Transactions on Multimedia is to integrate all aspects of multimedia systems and technology, signal processing, and applications. It will cover various aspects of research in multimedia technology and applications including, but not limited to: circuits, algorithms and macro/micro-architectures, software, detailed design, synchronization, interaction, joint processing and coordination of multimedia and multimodal signals/data, compression, storage, retrieval, communication, ...
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...
Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.
Sunwook Rhee; Changgeun Kim; Juhee Kim; Yong Jee Computer Engineering and Applications (ICCEA), 2010 Second International Conference on, 2010
In this paper, we propose a concatenated Reed-Solomon code with a Hamming code for dynamic random access memory (DRAM) controller. The concatenated code consists of a Reed-Solomon outer code, two shortened Reed-Solomon codes, and a Hamming inner code. The proposed code takes the advantages of Reed-Solomon codes and Hamming codes to protect DRAM memory data against single event upsets and ...
Perigny, R.; Un-Ku Moon; Temes, G. Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 2001
This paper describes the operation of three types of charge pump circuits. Power efficiency theory of charge pumps is discussed. A method of estimating the output ripple of a charge pump from the size of the capacitors used is described. A new charge pump circuit that uses two cascoded buffer transistors to improve the area efficiency is proposed
Jang, Weon Wi; Jeong Oen Lee; Yang, Hyun-Ho; Jun-Bo Yoon Electron Devices, IEEE Transactions on, 2008
We proposed and demonstrated a mechanically operated random access memory (MORAM) based on an electrostatically actuated metallic microswitch for nonvolatile memory applications. The metallic microswitch-based MORAM successfully showed program and erase operations, wherein the microswitch had an essentially zero off current, an abrupt switching with less than 1 mV/dec, and an on/off current ratio over 107, and its stored charge ...
Fukuda, Y.; Kato, K.; Umemura, E. Electrical Overstress/Electrostatic Discharge Symposium, 1996. Proceedings, 1996
As packing density of LSI (Large Scale Integrated circuits) is increasing, device geometry has to be miniaturized. For advanced LSI such as 16-64 Mbit DRAM (dynamic random access memory), gate length of MOS (metal oxide semiconductor) transistor becomes 0.3-0.5 micron. This scaling requires thin oxide film and shallow junction. On the other hand, it is well known that the scaling ...
Brent, Richard P. Frontiers of Massively Parallel Computation, 1992., Fourth Symposium on the, 1992
The author describes an implementation of the LINPACK benchmark on the Fujitsu AP 1000. Design considerations include communication primitives, data distribution, use of blocking to reduce memory references, and effective use of the cache. The LINPACK benchmark results show that the AP 1000 is a good machine for numerical linear algebra, and that one can consistently achieve close to 80 ...
Ellis, Wayne Effects of Reliability Mechanisms On VLSI Circuit Functionality, 2004
This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to ...
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