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Conferences related to DRAM chips

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2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments\, keynotes\, panels\, plus User Track presentations. A diverse worldwide community representing more than 1\,000 organization attends each year\, from system designers and architects\, logic and circuit designers\, validation engineers\, CAD managers\, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers. Analog Circuits [x] Analog/mixed-signal [x] Design For Manufacturability [x] Design Verification [x] Embedded Systems [x] Emerging Design Technologies [x] Fpga [x] Green Technology [x] High-level Synthesis [x] Interconnect [x] Low-power Design [x] Physical Design [x] Reconfigurable Computing [x] Reliability [x] Rf Design [x] Synthesis [x] System-level Design [x] Testing And Verification [x]


2012 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS)

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Performance and Power Analysis of Computer Systems and Software.


2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA)

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Processor, cache, memory, parallel, multicore, multiprocessor, power-efficient, reliable, secure, embedded, reconfigurable, heterogehous, network processor, interconnect and network interface, emerging, and/or high-performance architectures, Impact of technology on architecture, High-performance I/O systems, Hardware/software trade-offs, Impact of compilers and system software on architecture, Performance modeling, simulation, and projection techniques, applications.


IEEE EUROCON 2011 - International Conference on Computer as a Tool (EUROCON)

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Main topics: Telecommunications and Multimedia Systems; Information Technologies and Intelligent Systems; CIRCUITS AND SYSTEMS; POWER SYSTEMS AND RENEWABLE RESOURCES; EDUCATION; ENGINEERING MANAGEMENT To promote interaction between industry and academia contributions of recent industrial developments will be accepted and published in a maximum 1-page of abstract and 1-page of figures.


2010 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

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Application-specific systems: network computing, special-purpose systems, performance evaluation, design languages, compilers, operating systems, nanocomputing systems and applications, hardware/software integration and rapid prototyping. Application-specific architectures: special-purpose designs, design methodology, CAD tools, fault tolerance, specifications and interfaces, networks-on-a-chip, hardware/software co-design, processor arrays, SoC, superscalar, multithreaded, VLIW and EPIC architectures.

  • 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    The conference will cover the theory and practice of application-specific systems, architectures and processors. Areas for application-specific computing are many and varied. Some sample application areas include information systems, signal and image processing, multimedia systems, communication, high-speed networks, sensor networks, compression, graphics, cryptography, and many areas of computational science.


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Xplore Articles related to DRAM chips

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  • Exploration and Optimization of 3-D Integrated DRAM Subsystems

    Weis, C.; Loi, I.; Benini, L.; Wehn, N. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2013

    Energy efficiency is the major optimization criterion for systems-on-chip (SoCs) for mobile devices (smartphones and tablets). Through silicon via (TSV) technology enables 3-D integration of dies and the heterogeneous stacking of multiple memory or logic layers, allowing increased bandwidth and lower energy consumption of the memory interface compared to traditional approaches. In this paper, we explore the 3-D-DRAM architecture design ...

  • Hardware/software techniques for DRAM thermal management

    Song Liu; Leung, B.; Neckar, A.; Memik, S.O.; Memik, G.; Hardavellas, N. High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, 2011

    The performance of the main memory is an important factor on overall system performance. To improve DRAM performance, designers have been increasing chip densities and the number of memory modules. However, these approaches increase power consumption and operating temperatures: temperatures in existing DRAM modules can rise to over 95°C. Another important property of DRAM temperature is the large variation in ...

  • CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory

    Ke Chen; Sheng Li; Muralimanohar, N.; Ahn, Jung Ho; Brockman, J.B.; Jouppi, N.P. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, 2012

    Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future memory architectures to satisfy the ever-increasing demands on performance, power, and cost. This paper introduces CACTI-3DD, the first architecture-level integrated power, area, and timing modeling framework for 3D die-stacked off-chip DRAM main memory. CACTI-3DD includes TSV models, improves models for 2D off-chip DRAM main memory over ...

  • Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV

    Dong Hyuk Woo; Nak Hee Seong; Lee, H.-H.S. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2013

    As scaling DRAM cells becomes more challenging and energy-efficient DRAM chips are in high demand, the DRAM industry has started to undertake an alternative approach to address these looming issues-that is, to vertically stack DRAM dies with through-silicon-vias (TSVs) using 3-D-IC technology. Furthermore, this emerging integration technology also makes heterogeneous die stacking in one DRAM package possible. Such a heterogeneous ...

  • A study of DRAM failures in the field

    Sridharan, V.; Liberty, D. High Performance Computing, Networking, Storage and Analysis (SC), 2012 International Conference for, 2012

    Most modern computer systems use dynamic random access memory (DRAM) as a main memory store. Recent publications have confirmed that DRAM errors are a common source of failures in the field. Therefore, further attention to the faults experienced by DRAM sub-systems is warranted. In this paper, we present a study of 11 months of DRAM errors in a large high-performance ...

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Educational Resources on DRAM chips

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  • Effects of Reliability Mechanisms On VLSI Circuit Functionality

    Ellis, Wayne Effects of Reliability Mechanisms On VLSI Circuit Functionality, 2004

    This tutorial discusses examples of reliability mechanisms and how these can affect the normal operation of selected VLSI circuits. Large circuit-count ASIC chips use standard digital and analog circuits such as Logic gates, eSRAM, eDRAM and I/O circuits which must function properly under various voltage and thermal environments. These chips are subjected to Reliability Screens such as Burn In to ...


Standards related to DRAM chips

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No standards are currently tagged "DRAM chips"


Periodicals related to DRAM chips

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  • Solid-State Circuits, IEEE Journal of

    The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...

  • Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

    Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.