Conferences related to DRAM chips

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2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.


2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

Topics of interest include, but are not limited to:+Processor, cache, and memory architectures+Parallel computer architectures+Multicore architectures+Impact of technology on architecture+Power-efficient architectures and techniques+Dependable/secure architectures+High-performance I/O systems+Embedded and reconfigurable architectures+Interconnect and network interface architectures+Architectures for cloud-based HPC and data centers+Innovative hardware/software trade-offs+Impact of compilers and system software on architecture+Performance modeling and evaluation+Architectures for emerging technology and applications


2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP)

The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2013 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc.

  • 2012 IEEE 23rd International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    The conference will cover the theory and practice of application-specific systems, architectures and processors. The 2012 conference will build upon traditional strengths in areas such as arithmetic, cryptography, compression, signal and image processing, application-specific instruction processors, etc. We especially encourage submissions in the following three areas: Bioinformatics and computational biology - life sciences present a host of interesting problems that can benefit from application-specific solutions. Computational finance - the financial community has significant needs for high performance computing. Architecturally diverse systems - systems that use varied computing resources such as FPGAs, GPUs, Cell processors, etc.

  • 2010 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    Application-specific systems: network computing, special-purpose systems, performance evaluation, design languages, compilers, operating systems, nanocomputing systems and applications, hardware/software integration and rapid prototyping. Application-specific architectures: special-purpose designs, design methodology, CAD tools, fault tolerance, specifications and interfaces, networks-on-a-chip, hardware/software co-design, processor arrays, SoC, superscalar, multithreaded, VLIW and EPIC architectures.

  • 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

    The conference will cover the theory and practice of application-specific systems, architectures and processors. Areas for application-specific computing are many and varied. Some sample application areas include information systems, signal and image processing, multimedia systems, communication, high-speed networks, sensor networks, compression, graphics, cryptography, and many areas of computational science.


2013 IEEE International 3D Systems Integration Conference (3DIC)

Technologies for enabling 3D systems based on Through Silicon Vias.

  • 2011 IEEE International 3D Systems Integration Conference (3DIC)

    3DIC 2012 will cover all 3D Integration topics, including 3D process technology, materials, equipment, circuits technology, design and test methodology and applications. The conference invites authors and attendees to submit and interact with 3D integration researchers from all around the world.

  • 2010 IEEE International 3D Systems Integration Conference (3DIC)

    3DIC 2010 will cover all 3D Integration topics, including 3D process technology, materials, equipment, circuits technology, design methodology and applications.

  • 2009 3rd International Conference on 3D System Integration (3DIC)

    covers all the topics in 3DIC, including 3D process technology, materials, equipment, circuits technology, design methodology and applications.


IEEE EUROCON 2013

The IEEE Region 8 EuroCon 2013 Conference is a premier forum for the exchange of ideas, open and direct discussion on the development of the Circuits and Systems, Multimedia, Information and Communication Technology and energy and power systems. It has achieved a considerable success during the past seven editions covering majority of the fields in the area of electrical engineering.


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Periodicals related to DRAM chips

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Multimedia, IEEE Transactions on

The goal of IEEE Transactions on Multimedia is to integrate all aspects of multimedia systems and technology, signal processing, and applications. It will cover various aspects of research in multimedia technology and applications including, but not limited to: circuits, algorithms and macro/micro-architectures, software, detailed design, synchronization, interaction, joint processing and coordination of multimedia and multimodal signals/data, compression, storage, retrieval, communication, ...


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.



Most published Xplore authors for DRAM chips

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Xplore Articles related to DRAM chips

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A design and performance study of 3D packaging for high performance memory applications

I. Mohammed; Byong-Su Seol; S. Krishnan Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. IEEE/CPMT/SEMI 28th International, 2003

To address the performance and miniaturization challenges being faced by the packaging industry, a novel packaging methodology is presented in this paper. A 3D packaging methodology that leverages the existing CSP (Chip Scale Packaging) infrastructure to design and build memory solutions that is high performing and highly dense is presented. The design includes the individual device package design, the 3D ...


Total Ionizing Dose Effects on FinFET-Based Capacitor-Less 1T-DRAMs

En Xia Zhang; Daniel M. Fleetwood; Farah El-Mamouni; Michael L. Alles; Ronald D. Schrimpf; Weize Xiong; Chris Hobbs; Kerem Akarvardar; Sorin Cristoloveanu IEEE Transactions on Nuclear Science, 2010

We have characterized the total ionizing dose (TID) response of SOI FinFETs, fabricated in two different technologies, operated in 1T-DRAM mode, one with poly-crystalline Si gates and a SiO2 gate dielectric, and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage (GIDL) programming methods. 1T- DRAM ...


A Microprocessor for Speech Recognition

Y. Kawakami; H. Ishizuka; M. Watari; H. Sakoe; T. Hoshi; T. Iwata IEEE Journal on Selected Areas in Communications, 1985

A new single-chip microprocessor for speech recognition, the SRP, has been developed, utilizing a multiprocessor architecture and a pipelined structure. It can recognize up to 340 isolated words or 40 connected words in real time. The SRP contains a vector distance calculator, a DP-equation calculator, and an I/O controller operating in a pipelined manner. Algorithm variations and operation parameters are ...


Energy-efficient large-scale matrix multiplication on FPGAs

Kiran Kumar Matam; Viktor K. Prasanna 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013

Energy efficiency has emerged as one of the key performance metrics in computing. In this work, we present an energy efficient design for large-scale matrix multiplication. As a baseline architecture, we use a highly optimized on-chip matrix multiplication architecture extended to support large matrices using external memory. Based on the matrix multiplication algorithm and the DRAM model, we present an ...


DRAM variable retention time

P. J. Restle; J. W. Park; B. F. Lloyd Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International, 1992

A DRAM bit has variable retention time (VRT) when the memory cell leakage, which determines how long a cell can retain information, varies with time. This paper reports on a study of VRT in cells from 4Mbit and 16 Mbit DRAM chips produced by a variety of manufacturers and in a number of technologies including trench capacitor and stacked capacitor ...


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Educational Resources on DRAM chips

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eLearning

A design and performance study of 3D packaging for high performance memory applications

I. Mohammed; Byong-Su Seol; S. Krishnan Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. IEEE/CPMT/SEMI 28th International, 2003

To address the performance and miniaturization challenges being faced by the packaging industry, a novel packaging methodology is presented in this paper. A 3D packaging methodology that leverages the existing CSP (Chip Scale Packaging) infrastructure to design and build memory solutions that is high performing and highly dense is presented. The design includes the individual device package design, the 3D ...


Total Ionizing Dose Effects on FinFET-Based Capacitor-Less 1T-DRAMs

En Xia Zhang; Daniel M. Fleetwood; Farah El-Mamouni; Michael L. Alles; Ronald D. Schrimpf; Weize Xiong; Chris Hobbs; Kerem Akarvardar; Sorin Cristoloveanu IEEE Transactions on Nuclear Science, 2010

We have characterized the total ionizing dose (TID) response of SOI FinFETs, fabricated in two different technologies, operated in 1T-DRAM mode, one with poly-crystalline Si gates and a SiO2 gate dielectric, and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage (GIDL) programming methods. 1T- DRAM ...


A Microprocessor for Speech Recognition

Y. Kawakami; H. Ishizuka; M. Watari; H. Sakoe; T. Hoshi; T. Iwata IEEE Journal on Selected Areas in Communications, 1985

A new single-chip microprocessor for speech recognition, the SRP, has been developed, utilizing a multiprocessor architecture and a pipelined structure. It can recognize up to 340 isolated words or 40 connected words in real time. The SRP contains a vector distance calculator, a DP-equation calculator, and an I/O controller operating in a pipelined manner. Algorithm variations and operation parameters are ...


Energy-efficient large-scale matrix multiplication on FPGAs

Kiran Kumar Matam; Viktor K. Prasanna 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013

Energy efficiency has emerged as one of the key performance metrics in computing. In this work, we present an energy efficient design for large-scale matrix multiplication. As a baseline architecture, we use a highly optimized on-chip matrix multiplication architecture extended to support large matrices using external memory. Based on the matrix multiplication algorithm and the DRAM model, we present an ...


DRAM variable retention time

P. J. Restle; J. W. Park; B. F. Lloyd Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International, 1992

A DRAM bit has variable retention time (VRT) when the memory cell leakage, which determines how long a cell can retain information, varies with time. This paper reports on a study of VRT in cells from 4Mbit and 16 Mbit DRAM chips produced by a variety of manufacturers and in a number of technologies including trench capacitor and stacked capacitor ...


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