Conferences related to Memory

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2020 IEEE/ASME International Conference on Advanced Intelligent Mechatronics (AIM)

The scope of the 2020 IEEE/ASME AIM includes the following topics: Actuators, Automotive Systems, Bioengineering, Data Storage Systems, Electronic Packaging, Fault Diagnosis, Human-Machine Interfaces, Industry Applications, Information Technology, Intelligent Systems, Machine Vision, Manufacturing, Micro-Electro-Mechanical Systems, Micro/Nano Technology, Modeling and Design, System Identification and Adaptive Control, Motion Control, Vibration and Noise Control, Neural and Fuzzy Control, Opto-Electronic Systems, Optomechatronics, Prototyping, Real-Time and Hardware-in-the-Loop Simulation, Robotics, Sensors, System Integration, Transportation Systems, Smart Materials and Structures, Energy Harvesting and other frontier fields.


2019 56th ACM/IEEE Design Automation Conference (DAC)

EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM//IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2019 IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE SignalProcessing Society, is the premier forum for the presentation of technological advances andresearch results in the fields of theoretical, experimental, and applied image and videoprocessing. ICIP 2019, the 26th in the series that has been held annually since 1994, bringstogether leading engineers and scientists in image and video processing from around the world.


2019 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


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Periodicals related to Memory

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Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Audio, Speech, and Language Processing, IEEE Transactions on

Speech analysis, synthesis, coding speech recognition, speaker recognition, language modeling, speech production and perception, speech enhancement. In audio, transducers, room acoustics, active sound control, human audition, analysis/synthesis/coding of music, and consumer audio. (8) (IEEE Guide for Authors) The scope for the proposed transactions includes SPEECH PROCESSING - Transmission and storage of Speech signals; speech coding; speech enhancement and noise reduction; ...


Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


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Xplore Articles related to Memory

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A Cu<inf>x</inf>O-based resistive memory with low power and high reliability for SOC nonvolatile memory applications

[{u'author_order': 1, u'affiliation': u'ASIC and System State Key Laboratory, Research Center of Semiconductor Memory and Application, Fudan University, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37066484600', u'full_name': u'M. Wang', u'id': 37066484600}, {u'author_order': 2, u'affiliation': u'ASIC and System State Key Laboratory, Research Center of Semiconductor Memory and Application, Fudan University, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37579166800', u'full_name': u'Y. L. Song', u'id': 37579166800}, {u'author_order': 3, u'affiliation': u'ASIC and System State Key Laboratory, Research Center of Semiconductor Memory and Application, Fudan University, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37392479100', u'full_name': u'H.J. Wan', u'id': 37392479100}, {u'author_order': 4, u'affiliation': u'ASIC and System State Key Laboratory, Research Center of Semiconductor Memory and Application, Fudan University, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37533040100', u'full_name': u'H.B. Lv', u'id': 37533040100}, {u'author_order': 5, u'affiliation': u'ASIC and System State Key Laboratory, Research Center of Semiconductor Memory and Application, Fudan University, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37287970300', u'full_name': u'P. Zhou', u'id': 37287970300}, {u'author_order': 6, u'affiliation': u'ASIC and System State Key Laboratory, Research Center of Semiconductor Memory and Application, Fudan University, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37307092900', u'full_name': u'T. A. Tang', u'id': 37307092900}, {u'author_order': 7, u'affiliation': u'ASIC and System State Key Laboratory, Research Center of Semiconductor Memory and Application, Fudan University, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37405328400', u'full_name': u'Y. Y. Lin', u'id': 37405328400}, {u'author_order': 8, u'affiliation': u'SOC Technology Development Center, Semiconductor Manufacturing International Corp, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37532836900', u'full_name': u'R. Huang', u'id': 37532836900}, {u'author_order': 9, u'affiliation': u'SOC Technology Development Center, Semiconductor Manufacturing International Corp, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37533451000', u'full_name': u'S. Song', u'id': 37533451000}, {u'author_order': 10, u'affiliation': u'SOC Technology Development Center, Semiconductor Manufacturing International Corp, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37537247000', u'full_name': u'J. G. Wu', u'id': 37537247000}, {u'author_order': 11, u'affiliation': u'SOC Technology Development Center, Semiconductor Manufacturing International Corp, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37279672200', u'full_name': u'H. M. Wu', u'id': 37279672200}, {u'author_order': 12, u'affiliation': u'SOC Technology Development Center, Semiconductor Manufacturing International Corp, Shanghai, China', u'authorUrl': u'https://ieeexplore.ieee.org/author/37396592300', u'full_name': u'M. H. Chi', u'id': 37396592300}] 2010 IEEE International Memory Workshop, 2010

A CuxO-based resistive memory is successfully integrated in 0.13 μm logic process. Operation algorithm is optimized to achieve low power consumption with reset current down to 30 μA. High thermal stability and small cell size less than 22 F2have been demonstrated. The advantages make this device promising for system on chip non-volatile memory applications.


A 90nm 32-mb phase change memory with flash SPI compatibility

[{u'author_order': 1, u'affiliation': u'Being Advanced Memory Corporation Williston, Vermont 05495', u'full_name': u'Wolfgang Hokenmaier'}, {u'author_order': 2, u'affiliation': u'Being Advanced Memory Corporation Williston, Vermont 05495', u'full_name': u'Don Labrecque'}, {u'author_order': 3, u'affiliation': u'Being Advanced Memory Corporation Williston, Vermont 05495', u'full_name': u'Ryan Jurasek'}, {u'author_order': 4, u'affiliation': u'Being Advanced Memory Corporation Williston, Vermont 05495', u'full_name': u'Van Butler'}, {u'author_order': 5, u'affiliation': u'Being Advanced Memory Corporation Williston, Vermont 05495', u'full_name': u'Chris Scoville'}, {u'author_order': 6, u'affiliation': u'Being Advanced Memory Corporation Williston, Vermont 05495', u'full_name': u'Aaron Willey'}, {u'author_order': 7, u'affiliation': u'Being Advanced Memory Corporation Williston, Vermont 05495', u'full_name': u'Steffen Loeffler'}, {u'author_order': 8, u'affiliation': u'Being Advanced Memory Corporation Williston, Vermont 05495', u'full_name': u'Yuanxing Li'}, {u'author_order': 9, u'affiliation': u'Being Advanced Memory Corporation Williston, Vermont 05495', u'full_name': u'Sourabh Sharma'}] 2014 IEEE 6th International Memory Workshop (IMW), 2014

A 32-Mb Phase Change Memory is realized in a 90nm 6-Metal process. An erase speed of 10.0-Mb/second and program speed of 35.6-Mb/second is achieved. The cell retention is interpolated to be 10 years at 85°C and cell endurance is measured to be 109cycles. The 25F2mushroom cell phase change memory utilizes a planar transistor. An ECC solution is employed to correct ...


Modeling and Characterization of Program / Erasure Speed and Retention of TiN-gate MANOS (Si-Oxide-SiNx-Al2O3-Metal Gate) Cells for NAND Flash Memory

[{u'author_order': 1, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399 E-mail:eunseok.choi@hynix.com', u'authorUrl': u'https://ieeexplore.ieee.org/author/38597226700', u'full_name': u'Eun-Seok Choi', u'id': 38597226700}, {u'author_order': 2, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37852907800', u'full_name': u'Hyun-Seung Yoo', u'id': 37852907800}, {u'author_order': 3, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37935576600', u'full_name': u'Kyoung-Hwan Park', u'id': 37935576600}, {u'author_order': 4, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37291919000', u'full_name': u'Se-Jun Kim', u'id': 37291919000}, {u'author_order': 5, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37576901100', u'full_name': u'Jung-Ryul Ahn', u'id': 37576901100}, {u'author_order': 6, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37934254900', u'full_name': u'Myung-Shik Lee', u'id': 37934254900}, {u'author_order': 7, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37932263400', u'full_name': u'Young-Ok Hong', u'id': 37932263400}, {u'author_order': 8, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37933856900', u'full_name': u'Suk-Goo Kim', u'id': 37933856900}, {u'author_order': 9, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37408035200', u'full_name': u'Jae-Chul Om', u'id': 37408035200}, {u'author_order': 10, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37272278800', u'full_name': u'Moon-Sig Joo', u'id': 37272278800}, {u'author_order': 11, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37563781500', u'full_name': u'Seung-Ho Pyi', u'id': 37563781500}, {u'author_order': 12, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37736099700', u'full_name': u'Seaung-Suk Lee', u'id': 37736099700}, {u'author_order': 13, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37281163400', u'full_name': u'Seok-Kiu Lee', u'id': 37281163400}, {u'author_order': 14, u'affiliation': u'Mobile & Flash Memory Division, Hynix Semiconductor Inc., San 136-1, Ami-ri, Bubal-eup, Ichon-si Kyoungki-do, 476-701, Korea, Phone:+82-31-630-2819 Fax:+82-31-630-5399', u'authorUrl': u'https://ieeexplore.ieee.org/author/37265986400', u'full_name': u'Gi-Hyun Bae', u'id': 37265986400}] 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, 2007

In this study, physical properties of different trapping nitrides were extracted, and the program efficiency of MANOS cell was explained. We also showed shallow traps were generated at trapping nitride by etching damage, and this could be cured resulting great improvement of cell performance. Lastly, erasure mechanism of TiN-gate MANOS cell was discussed with some experimental and modeling results.


3-dimensional analysis on the cell string current of NAND flash memory

[{u'author_order': 1, u'affiliation': u'Semicond. R&D Center, Memory Bus., Samsung Electron. Co., Ltd., Yongin, South Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37895994300', u'full_name': u'H.-S. Oh', u'id': 37895994300}, {u'author_order': 2, u'affiliation': u'Semicond. R&D Center, Memory Bus., Samsung Electron. Co., Ltd., Yongin, South Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/38185736300', u'full_name': u'S.-C. Lee', u'id': 38185736300}, {u'author_order': 3, u'affiliation': u'Semicond. R&D Center, Memory Bus., Samsung Electron. Co., Ltd., Yongin, South Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37280407500', u'full_name': u'C.-S. Lee', u'id': 37280407500}, {u'author_order': 4, u'affiliation': u'Semicond. R&D Center, Memory Bus., Samsung Electron. Co., Ltd., Yongin, South Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37898270800', u'full_name': u'D.-Y. Oh', u'id': 37898270800}, {u'author_order': 5, u'affiliation': u'Semicond. R&D Center, Memory Bus., Samsung Electron. Co., Ltd., Yongin, South Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37367406800', u'full_name': u'T.-K. Kim', u'id': 37367406800}, {u'author_order': 6, u'affiliation': u'Semicond. R&D Center, Memory Bus., Samsung Electron. Co., Ltd., Yongin, South Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37348950200', u'full_name': u'J.-H. Song', u'id': 37348950200}, {u'author_order': 7, u'affiliation': u'Semicond. R&D Center, Memory Bus., Samsung Electron. Co., Ltd., Yongin, South Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37337432900', u'full_name': u'K.-H. Lee', u'id': 37337432900}, {u'author_order': 8, u'affiliation': u'Semicond. R&D Center, Memory Bus., Samsung Electron. Co., Ltd., Yongin, South Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37367829300', u'full_name': u'Y.-K. Park', u'id': 37367829300}, {u'author_order': 9, u'affiliation': u'Semicond. R&D Center, Memory Bus., Samsung Electron. Co., Ltd., Yongin, South Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37367090900', u'full_name': u'J.-H. Choi', u'id': 37367090900}, {u'author_order': 10, u'affiliation': u'Semicond. R&D Center, Memory Bus., Samsung Electron. Co., Ltd., Yongin, South Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37277188600', u'full_name': u'J.-T. Kong', u'id': 37277188600}] Symposium Non-Volatile Memory Technology 2005., 2005

The cell string current of NAND flash memory is very small due to large resistance from the cells connected in series. In this paper, scaling effects on the cell current are analyzed for 70/60/50 nm NAND flash technologies using 3-dimensional TCAD simulation. The geometrical and process parameters are varied and their effects are quantified. It is identified that the coupling ...


Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications

[{u'author_order': 1, u'affiliation': u'Process Development Team, Memory R&D Center, Semiconductor Business, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37887943200', u'full_name': u'Hong Sik Yoon', u'id': 37887943200}, {u'author_order': 2, u'affiliation': u'Process Development Team, Memory R&D Center, Semiconductor Business, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37270452400', u'full_name': u'In-Gyu Baek', u'id': 37270452400}, {u'author_order': 3, u'affiliation': u'Process Development Team, Memory R&D Center, Semiconductor Business, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37695370600', u'full_name': u'Jinshi Zhao', u'id': 37695370600}, {u'author_order': 4, u'affiliation': u'Process Development Team, Memory R&D Center, Semiconductor Business, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37430257600', u'full_name': u'Hyunjun Sim', u'id': 37430257600}, {u'author_order': 5, u'affiliation': u'Process Development Team, Memory R&D Center, Semiconductor Business, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37887940800', u'full_name': u'Min Young Park', u'id': 37887940800}, {u'author_order': 6, u'affiliation': u'Process Development Team, Memory R&D Center, Semiconductor Business, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37067370300', u'full_name': u'Hansin Lee', u'id': 37067370300}, {u'author_order': 7, u'affiliation': u'Process Development Team, Memory R&D Center, Semiconductor Business, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37534892700', u'full_name': u'Gyu-Hwan Oh', u'id': 37534892700}, {u'author_order': 8, u'affiliation': u'Process Development Team, Memory R&D Center, Semiconductor Business, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37887942100', u'full_name': u'Jong Chan Shin', u'id': 37887942100}, {u'author_order': 9, u'affiliation': u'Process Development Team, Memory R&D Center, Semiconductor Business, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37285728300', u'full_name': u'In-Seok Yeo', u'id': 37285728300}, {u'author_order': 10, u'affiliation': u'Process Development Team, Memory R&D Center, Semiconductor Business, Samsung Electronics Co. Ltd., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea', u'authorUrl': u'https://ieeexplore.ieee.org/author/37268314200', u'full_name': u'U-In Chung', u'id': 37268314200}] 2009 Symposium on VLSI Technology, 2009

Vertically defined resistance change memory cells for the vertical cross-point architecture (VCPA) as a high density non-volatile memory application are successfully demonstrated with a NiO switching layer. They showed both unipolar and bipolar switching mode. Several issues in realization for VCPA and their possible solutions are discussed.


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Educational Resources on Memory

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IEEE.tv Videos

IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
High-Bandwidth Memory Interface Design
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
The Memory of Cars Talk by Tom Coughlin
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
IEEE Medal of Honor Recipient (2009): Dr. Robert Dennard
Accelerating Machine Learning with Non-Volatile Memory: Exploring device and circuit tradeoffs - Pritish Narayanan: 2016 International Conference on Rebooting Computing
Quantum Photonic Networks for Computing and Simulation - Plenary Speaker: Ian Walmsley - IPC 2018
Improved Deep Neural Network Hardware Accelerators Based on Non-Volatile-Memory: the Local Gains Technique: IEEE Rebooting Computing 2017
Ted Berger: Far Futures Panel - Technologies for Increasing Human Memory - TTM 2018
Spin Dynamics in Inhomogeneously Magnetized Systems - Teruo Ono: IEEE Magnetics Society Distinguished Lecture 2016
The Superstrider Architecture: Integrating Logic and Memory towards non-von Neumann Computing: IEEE Rebooting Computing 2017
Raspberry Pi High Speed SerDes Characterization Platform
Impact of Linearity and Write Noise of Analog Resistive Memory: IEEE Rebooting Computing 2017
NNgine: Ultra-Efficient Nearest Neighbor Accelerator Based on In-Memory Computing: IEEE Rebooting Computing 2017
IMS 2014: Dr. Rudolph Henning Memorial
Electrically-Pumped 1.31 μm MQW Lasers by Direct Epitaxy on Wafer-Bonded InP-on-SOI Substrate - Yingtao Hu - Closing Ceremony, IPC 2018
Array storing and retrieval
2015 IEEE Honors: IEEE Richard W. Hamming Medal - Imre Csiszar

IEEE-USA E-Books

  • Resistive Random Access Memory (RRAM)

    RRAM technology has made significant progress in the past decade as a competitive candidate for the next generation non-volatile memory (NVM). This lecture is a comprehensive tutorial of metal oxide-based RRAM technology from device fabrication to array architecture design. State-of-the-art RRAM device performances, characterization, and modeling techniques are summarized, and the design considerations of the RRAM integration to large-scale array with peripheral circuits are discussed. Chapter 2 introduces the RRAM device fabrication techniques and methods to eliminate the forming process, and will show its scalability down to sub-10 nm regime. Then the device performances such as programming speed, variability control, and multi-level operation are presented, and finally the reliability issues such as cycling endurance and data retention are discussed. Chapter 3 discusses the RRAM physical mechanism, and the materials characterization techniques to observe the conductive filaments and the electrical characterization techniques to study the electronic conduction processes. It also presents the numerical device modeling techniques for simulating the evolution of the conductive filaments as well as the compact device modeling techniques for circuit-level design. Chapter 4 discusses the two common RRAM array architectures for large-scale integration: one-transistor-one-resistor (1T1R) and cross-point architecture with selector. The write/read schemes are presented and the peripheral circuitry design considerations are discussed. Finally, a 3D integration approach is introduced for building ultra-high density RRAM array. Chapter 5 is a brief summary and will give an outlook for RRAM’s potential novel applications beyond the NVM applications.

  • Principles of Transactional Memory

    Transactional memory (TM) is an appealing paradigm for concurrent programming on shared memory architectures. With a TM, threads of an application communicate, and synchronize their actions, via in-memory transactions. Each transaction can perform any number of operations on shared data, and then either commit or abort. When the transaction commits, the effects of all its operations become immediately visible to other transactions; when it aborts, however, those effects are entirely discarded. Transactions are atomic: programmers get the illusion that every transaction executes all its operations instantaneously, at some single and unique point in time. Yet, a TM runs transactions concurrently to leverage the parallelism offered by modern processors. The aim of this book is to provide theoretical foundations for transactional memory. This includes defining a model of a TM, as well as answering precisely when a TM implementation is correct, what kind of properties it can ensure, what are the power and limitations of a TM, and what inherent trade-offs are involved in designing a TM algorithm. While the focus of this book is on the fundamental principles, its goal is to capture the common intuition behind the semantics of TMs and the properties of existing TM implementations. Table of Contents: Introduction / Shared Memory Systems / Transactional Memory: A Primer / TM Correctness Issues / Implementing a TM / Further Reading / Opacity / Proving Opacity: An Example / Opacity vs.\ Atomicity / Further Reading / The Liveness of a TM / Lock-Based TMs / Obstruction-Free TMs / General Liveness of TMs / Further Reading / Conclusions

  • The Memory System

    Today, computer-system optimization, at both the hardware and software levels, must consider the details of the memory system in its analysis; failing to do so yields systems that are increasingly inefficient as those systems become more complex. This lecture seeks to introduce the reader to the most important details of the memory system; it targets both computer scientists and computer engineers in industry and in academia. Roughly speaking, computer scientists are the users of the memory system and computer engineers are the designers of the memory system. Both can benefit tremendously from a basic understanding of how the memory system really works: the computer scientist will be better equipped to create algorithms that perform well and the computer engineer will be better equipped to design systems that approach the optimal, given the resource limitations. Currently, there is consensus among architecture researchers that the memory system is "the bottleneck," and this consensus has held for over a decade. Somewhat inexplicably, most of the research in the field is still directed toward improving the CPU to better tolerate a slow memory system, as opposed to addressing the weaknesses of the memory system directly. This lecture should get the bulk of the computer science and computer engineering population up the steep part of the learning curve. Not every CS/CE researcher/developer needs to do work in the memory system, but, just as a carpenter can do his job more efficiently if he knows a little of architecture, and an architect can do his job more efficiently if he knows a little of carpentry, giving the CS/CE worlds better intuition about the memory system should help them build better systems, both software and hardware. Table of Contents: Primers / It Must Be Modeled Accurately / ...\ and It Will Change Soon

  • Algorithms and Data Structures for External Memory

    Data sets in large applications are often too massive to fit completely inside the computer's internal memory. The resulting input/output communication (or I/O) between fast internal memory and slower external memory (such as disks) can be a major performance bottleneck. Algorithms and Data Structures for External Memory surveys the state of the art in the design and analysis of external memory (or EM) algorithms and data structures, where the goal is to exploit locality in order to reduce the I/O costs. A variety of EM paradigms are considered for solving batched and online problems efficiently in external memory. Algorithms and Data Structures for External Memory describes several useful paradigms for the design and implementation of efficient EM algorithms and data structures. The problem domains considered include sorting, permuting, FFT, scientific computing, computational geometry, graphs, databases, geographic information systems, and text and string processing. Algorithms and Data Structures for External Memory is an invaluable reference for anybody interested in, or conducting research in the design, analysis, and implementation of algorithms and data structures.

  • Flash Memory Reliability

    This chapter contains sections titled: * Introduction * Cycling-Induced Degradations in Flash Memories * Flash Memory Data Retention * Flash Memory Disturbs * Stress-Induced Tunnel Oxide Leakage Current * Special Reliability Issues for Poly-to-Poly Erase and Source-Side Injection Program * Process Impacts on Flash Memory Reliability * High-Voltage Periphery Transistor Reliability * Design and System Impacts on Flash Memory Reliability * Flash Memory Reliability Screening and Qualification * For Further Study * References ]]>

  • A Primer on Memory Consistency and Cache Coherence

    Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies

  • Supporting and Exploiting Spatial Memory in User Interfaces

    Spatial memory is an important facet of human cognition - it allows users to learn the locations of items over time and retrieve them with little effort. In human-computer interfaces, a strong knowledge of the spatial location of controls can enable a user to interact fluidly and efficiently, without needing to visually search for relevant controls. Computer interfaces should therefore be designed to provide support for developing the user's spatial memory, and they should allow the user to exploit it for rapid interaction whenever possible. However, existing systems offer varying support for spatial memory. Many modern interfaces break the user's ability to remember spatial locations, by moving or re-arranging items; others leave spatial memory underutilised, requiring slow sequences of mechanical actions to select items rather than exploiting users' strong ability to index items and controls by their on-screen locations. Supporting and Exploiting Spatial Memory in User Interfaces highlights the importance of designing for spatial memory in HCI. It summarizes empirical results on spatial memory from both the psychology and HCI domains, identifying a set of observable properties of spatial memory that can be used to inform design. It also analyses existing interfaces in the HCI literature that support or disrupt spatial memory, including space-multiplexed displays for command and navigation interfaces, different techniques for dealing with large spatial data sets, and the effects of spatial distortion. Supporting and Exploiting Spatial Memory in User Interfaces provides strong evidence that spatial knowledge of controls and data enables rapid interaction and information retrieval, and allows users to focus more of their cognitive resources on the task at hand, rather than on the interface. It is aimed at user interface designers, as well as other HCI researchers interested in spatial memory. Useful guidelines for designers are identified throughout the book, which provide clear advice on how and when to design with spatial memory in mind. Similarly, the concluding summary of the area, as well as methodological cautions and directions for future research provide an excellent resource for scientists interested in the importance of spatial memory in user interfaces.

  • A Primer on Compression in the Memory Hierarchy

    This synthesis lecture presents the current state-of-the-art in applying low- latency, lossless hardware compression algorithms to cache, memory, and the memory/cache link. There are many non-trivial challenges that must be addressed to make data compression work well in this context. First, since compressed data must be decompressed before it can be accessed, decompression latency ends up on the critical memory access path. This imposes a significant constraint on the choice of compression algorithms. Second, while conventional memory systems store fixed-size entities like data types, cache blocks, and memory pages, these entities will suddenly vary in size in a memory system that employs compression. Dealing with variable size entities in a memory system using compression has a significant impact on the way caches are organized and how to manage the resources in main memory. We systematically discuss solutions in the open literature to these problems. Chapter 2 provides the foundations of data compression by first introducing the fundamental concept of value locality. We then introduce a taxonomy of compression algorithms and show how previously proposed algorithms fit within that logical framework. Chapter 3 discusses the different ways that cache memory systems can employ compression, focusing on the trade-offs between latency, capacity, and complexity of alternative ways to compact compressed cache blocks. Chapter 4 discusses issues in applying data compression to main memory and Chapter 5 covers techniques for compressing data on the cache-to-memory links. This book should help a skilled memory system designer understand the fundamental challenges in applying compression to the memory hierarchy and introduce him/her to the state-of-the-art techniques in addressing them.

  • Non-Volatile In-Memory Computing by Spintronics

    Exa-scale computing needs to re-examine the existing hardware platform that can support intensive data-oriented computing. Since the main bottleneck is from memory, we aim to develop an energy-efficient in-memory computing platform in this book. First, the models of spin-transfer torque magnetic tunnel junction and racetrack memory are presented. Next, we show that the spintronics could be a candidate for future data-oriented computing for storage, logic, and interconnect. As a result, by utilizing spintronics, in- memory-based computing has been applied for data encryption and machine learning. The implementations of in-memory AES, Simon cipher, as well as interconnect are explained in details. In addition, in-memory-based machine learning and face recognition are also illustrated in this book.

  • Main Memory Database Systems

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Standards related to Memory

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IEEE Standard for Authenticated Encryption with Length Expansion for Storage Devices

This standard specifies requirements for cryptographic units that provide encryption and authentication for data contained within storage media. Full interchange requires additional format specifications (such as compression algorithms and physical data format) that are beyond the scope of this standard.


IEEE Standard for Communicating Among Processors and Peripherals Using Shared Memory (Direct Memory Access - DMA)


IEEE Standard for Cryptographic Protection of Data on Block-Oriented Storage Devices

This standard specifies elements of an architecture for cryptographic protection of data on block-oriented storage devices, describing the methods, algorithms, and modes of data protection to be used.


IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink)

Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory ...


IEEE Standard for Scalable Storage Interface

This standard defines a scalable interface for use with memory-mapped storage units and other devices. The term storage unit" can encompass rotating


More Standards