Conferences related to Memory

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2018 IEEE Symposium on VLSI Circuits

Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2020 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2016 IEEE Symposium on VLSI Circuits

    circuit design to address challenges of deeply scaled technologies - e.g. dfm, variability, reliability - digital circuit techniques - analog and mixed signal circuits such as data converters and amp

  • 2014 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2012 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation

  • 2011 Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2010 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2009 Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies

  • 2008 IEEE Symposium on VLSI Circuits

  • 2007 IEEE Symposium on VLSI Circuits


2018 IEEE Symposium on VLSI Technology

New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2020 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2016 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2014 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2012 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2011 Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2010 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2009 IEEE Symposium on VLSI Technology

    - New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D-system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices

  • 2008 IEEE Symposium on VLSI Technology

  • 2007 IEEE Symposium on VLSI Technology

  • 2006 IEEE Symposium on VLSI Technology


2017 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

  • 2021 IEEE International Electron Devices Meeting (IEDM)

    the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

  • 2019 IEEE International Electron Devices Meeting (IEDM)

    the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

  • 2015 IEEE International Electron Devices Meeting (IEDM)

    the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart-power technologies, etc.

  • 2014 IEEE International Electron Devices Meeting (IEDM)

    IEDM is the world s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.

  • 2013 IEEE International Electron Devices Meeting (IEDM)

    IEDM is the world s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.

  • 2012 IEEE International Electron Devices Meeting (IEDM)

  • 2011 IEEE International Electron Devices Meeting (IEDM)

    CMOS Devices Technology, Characterization, Reliability and Yield, Displays, sensors and displays, memory technology, modeling and simulation, process technology, solid state and nanoelectronic devices.

  • 2010 IEEE International Electron Devices Meeting (IEDM)

  • 2009 IEEE International Electron Devices Meeting (IEDM)

    CMOS Devices Technology, Characterization, REliability and Yield, Displays, sensors and displays, memory technology, modeling and simulation, process technology, solid state and nanoelectronic devices

  • 2008 IEEE International Electron Devices Meeting (IEDM)

    Over the last 53 years, the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart-power technologies, etc.

  • 2007 IEEE International Electron Devices Meeting (IEDM)

  • 2006 IEEE International Electron Devices Meeting (IEDM)


2017 IEEE International Solid- State Circuits Conference - (ISSCC)

The International Solid-State Circuits Conference is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS IC's.


2015 IEEE International Reliability Physics Symposium (IRPS)

Sharing information related to cause, effects and solutions in the deign and manufacture of electronics and related components


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Periodicals related to Memory

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Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


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Xplore Articles related to Memory

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A Multi-Solver Scheme Based on Combined Field Integral Equations for Electromagnetic Modeling of Highly Complex Objects

Jian Guan; Su Yan; Jian-Ming Jin IEEE Transactions on Antennas and Propagation, 2017

A combined field integral equation (CFIE)-based multisolver scheme is presented for electromagnetic modeling of objects with complex structures and materials. In this scheme, an object is decomposed into multiple bodies based on its material property and geometry. To model bodies with complicated materials, the finite element-boundary integral (FE-BI) method is applied. To model bodies with homogeneous or conducting materials, the ...


Arithmetic and galois checksums

N. R. Saxena; E. J. McCluskey 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 1989

An analysis is presented of error detection characteristics when galois checksums and arithmetic checksums are used simultaneously. By generalizing previous results, it is shown that galois checksums and arithmetic checksums exhibit orthogonal characteristics with respect to error detection. An analytic proof of orthogonality is presented for certain restricted cases. These orthogonal characteristics hold good for equally likely errors, restricted column ...


Introduction to the Issue on Progress in Solid-State, Fiber, and Tunable Sources

Ramesh K. Shori; Kenneth L. Schepler; W. Andrew Clarkson IEEE Journal of Selected Topics in Quantum Electronics, 2007

The 42 papers in this special issue are focused on progress in solid-state, fiber, and tunable sources. The issue is dedicated to the memory of Theodore H. Maiman, who kicked off the rapid growth of solid-state laser development in 1960. The papers are organized into six subject areas: power scaling strategies; fiber lasers and amplifiers; thin-disk lasers; planar waveguide and ...


Implementation methodology of acoustic echo cancellation based on FELMS adaptive algorithm

A. Zergainoh Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

The paper presents a unified methodology for an efficient Digital Signal Processor (DSP) implementation of acoustic echo cancellation algorithm based on the Fast Exact Least Mean Square (FELMS) adaptive algorithms. The difficulty is to retain as much as possible the improvement brought by the reduction of the arithmetic complexity of FELMS adaptive algorithms without exceeding DSP resources such as pointer ...


A new compact control unit for CNC using SoCs technology

Kh. M. Assar; I. S. Ashour; E. M. Saad; A. M. Rashid Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442), 2003

This paper introduces a new complete design and implementation of a System on Chip (SoC) control unit for three dimensions CNC, using FPGA technology. Intelligent controlling software is designed and integrated in the system using a standard HPGL format. A new communication strategy for optimum utilization of the required integrated memory is introduced and implemented. The new SoC design has ...


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Educational Resources on Memory

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eLearning

A Multi-Solver Scheme Based on Combined Field Integral Equations for Electromagnetic Modeling of Highly Complex Objects

Jian Guan; Su Yan; Jian-Ming Jin IEEE Transactions on Antennas and Propagation, 2017

A combined field integral equation (CFIE)-based multisolver scheme is presented for electromagnetic modeling of objects with complex structures and materials. In this scheme, an object is decomposed into multiple bodies based on its material property and geometry. To model bodies with complicated materials, the finite element-boundary integral (FE-BI) method is applied. To model bodies with homogeneous or conducting materials, the ...


Arithmetic and galois checksums

N. R. Saxena; E. J. McCluskey 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 1989

An analysis is presented of error detection characteristics when galois checksums and arithmetic checksums are used simultaneously. By generalizing previous results, it is shown that galois checksums and arithmetic checksums exhibit orthogonal characteristics with respect to error detection. An analytic proof of orthogonality is presented for certain restricted cases. These orthogonal characteristics hold good for equally likely errors, restricted column ...


Introduction to the Issue on Progress in Solid-State, Fiber, and Tunable Sources

Ramesh K. Shori; Kenneth L. Schepler; W. Andrew Clarkson IEEE Journal of Selected Topics in Quantum Electronics, 2007

The 42 papers in this special issue are focused on progress in solid-state, fiber, and tunable sources. The issue is dedicated to the memory of Theodore H. Maiman, who kicked off the rapid growth of solid-state laser development in 1960. The papers are organized into six subject areas: power scaling strategies; fiber lasers and amplifiers; thin-disk lasers; planar waveguide and ...


Implementation methodology of acoustic echo cancellation based on FELMS adaptive algorithm

A. Zergainoh Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

The paper presents a unified methodology for an efficient Digital Signal Processor (DSP) implementation of acoustic echo cancellation algorithm based on the Fast Exact Least Mean Square (FELMS) adaptive algorithms. The difficulty is to retain as much as possible the improvement brought by the reduction of the arithmetic complexity of FELMS adaptive algorithms without exceeding DSP resources such as pointer ...


A new compact control unit for CNC using SoCs technology

Kh. M. Assar; I. S. Ashour; E. M. Saad; A. M. Rashid Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442), 2003

This paper introduces a new complete design and implementation of a System on Chip (SoC) control unit for three dimensions CNC, using FPGA technology. Intelligent controlling software is designed and integrated in the system using a standard HPGL format. A new communication strategy for optimum utilization of the required integrated memory is introduced and implemented. The new SoC design has ...


More eLearning Resources

IEEE.tv Videos

IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
The Memory of Cars Talk by Tom Coughlin
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
IEEE Medal of Honor Recipient (2009): Dr. Robert Dennard
Accelerating Machine Learning with Non-Volatile Memory: Exploring device and circuit tradeoffs - Pritish Narayanan: 2016 International Conference on Rebooting Computing
Spin Dynamics in Inhomogeneously Magnetized Systems - Teruo Ono: IEEE Magnetics Society Distinguished Lecture 2016
IMS 2014: Dr. Rudolph Henning Memorial
Robotics History: Narratives and Networks Oral Histories: Barbara Hayes Roth
Array storing and retrieval
Neural Cognitive Robot: Learning, Memory and Intelligence
Jaynie Shorb from Broadcom at WIE ILC 2016
2015 IEEE Honors: IEEE Richard W. Hamming Medal - Imre Csiszar
Rebooting Computing Panel - Stan Williams: 2016 Technology Time Machine
35 Years of Magnetic Heterostructures
Digital Neuromorphic Design of a Liquid State Machine for Real-Time Processing - Nicholas Soures: 2016 International Conference on Rebooting Computing
IEEE @ SXSW 2015 - DIY Brain Hacking: Electroceuticals & You
Brooklyn 5G Summit 2014: Unleashing Millimeter-Wave Frequency by Andreas Roessler
MicroApps: Memory Effect Enhancements for X-Parameter Models in ADS (Agilent Technologies)
Magnetic Nanowires: Revolutionizing Hard Drives, RAM, and Cancer Treatment

IEEE-USA E-Books

  • Digging Yourself into a Hole: Put Down the Shovel and Seek Outside Help

    This chapter contains sections titled: The Memory Board The Cracked Solder Warning Signs that Someone is Digging a Hole Stop the Digging Conclusions about Digging Holes

  • Memory Management of Constraints in Flang

    A new implementation technique for a logic language extended by constraint handling tools is discussed. A special approach to memory management is introduced. This approach has been applied to the implementation of an extended version of a functional-logic language Flang. It has improved performance of the Flang system and permitted to incorporate important optiniizations, for instance, an intelligent backtracking strategy. Efficiency of the considered approach is shown.

  • TwoWay Communication Channels

    This chapter contains sections titled: Introduction Summary of results Basic definitions Average mutual information rates The distribution of information Random codes for the two-way channel Error probability for the ensemble of codes The convex hull G 1 as an inner bound of the capacity region An outer bound on the capacity region The concavity of R 12 and R 21 as functions of P(x1x2) Applications of the concavity property; channels with symmetric structure Nature of the region attainable in the outer bound An example where the inner and outer bounds differ Attainment of the outer bound with dependent sources General solution for the capacity region in the two-way channel Two-way channels with memory Generalization to T-terminal channels Appendix Error Probability Bounds in Terms of Moment Generating Functions References

  • Methods of Mapping from Phase to Sine Amplitude in Direct Digital Synthesis

    The are many methods for performing functional mapping from phase to sine amplitude (e.g., ROM look-up, course/fine segmentation into multiple ROM's, Taylor series, CORDIC algorithm). The spectral purity of the conventional direct digita1 synthesizer (DDS) is also determined by tile resolution of the values stored in the sine table ROM. Therefore, it is desirable co Increase the resolution of the ROM. Unfortunately, larger ROM. storage means higher. power consumption, lower reliability, lower speed, and greatly increased costs. Different memory compression and algorithmic techniques and their effect on distortion and trade-offs are Investigated in detail. A computer program has been created to simulate the effects of the memory compression and algorithmic techniques or the output: spectrum of the DDS. For each memory compression and algorithmic technique, the worst case spurious response is calculated using the computer program.

  • Thread Scheduling for Out-of-Core Applications with a Memory Server

    This chapter contains sections titled: The Memory Server Model, Fine-Grained Thread Scheduling, Implementation, Performance, Related Work, Conclusions and Limitations, Acknowledgments

  • Information Theory Basics

    This chapter contains sections titled: Issues in Information Theory. Additive White Gaussian Noise Channel Information of a Source Average Information of Discrete Memoryless Sources Source Coding for a Discrete Memoryless Source Entropy of Discrete Sources Exhibiting Memory Examples Generating Model Sources Run-Length Coding for Discrete Sources Exhibiting Memory Information Transmission via Discrete Channels Capacity of Discrete Channels Shannon's Channel Coding Theorem Capacity of Continuous Channels Shannon's Message for Wireless Channels Summary and Conclusions

  • Distributed Shared Memory

    This chapter contains sections titled: Introduction General Architecture of DSM Systerns Design and Implementation Issues of DSM Granularity Structure of Shared-Memory Space Consistency Models Replacement Strategy Thrashing Other Approaches to DSM Heterogeneous DSM Advantages of DSM Summary This chapter contains sections titled: Exercises Bibliography Pointers to Bibliographies on the Internet

  • An Air Defense System

    This chapter contains sections titled: The Whirlwind Computer, The New Missian, A Better Memory, Selecting IBM, Working Together, The SAGE System, Programming, An Assessment

  • Introduction to Remote Memory Operations

    This chapter contains sections titled: 3.1 Introduction, 3.2 Contrast with Message Passing, 3.3 Memory Windows, 3.4 Moving Data, 3.5 Completing RMA Data Transfers, 3.6 Examples of RMA Operations, 3.7 Pitfalls in Accessing Memory, 3.8 Performance Tuning for RMA Operations

  • CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Spectrum Communications

    Using a 3.5 $micro;m gate length complementary metal-oxidesemiconductor /silicon-on-sapphire (CMOS/80S) technology, a singlechip, radiation-hardened, direct digital frequency synthesizer has been developed. The circuit is a critical component of a fast-tuning wideband frequency synthesizer for spread spectrum satellite communications. Each clock period, the chip generates a new digitized sample of a sine wave, whose frequency is variable in 220 steps from dc to one-half the clock frequency. Operation at up to 7.5 MHz is possible in a worst case environment, including ionizing radiation levels up to 3 x 105 rads(Si). A computationally efficient algorithm was chosen, resulting in 12-bit output precision with only 1084 logic gates and 3840 bits of on-chip read-only memory (ROM). The accuracy of the algorithm is sufficient to maintain in-band spurious frequency components below  - 65 dDc. At 300 mW, the chip replaces an MSI implementation which uses 25 integrated circuits and consumes 3.5 W.



Standards related to Memory

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IEEE Standard for Authenticated Encryption with Length Expansion for Storage Devices

This standard specifies requirements for cryptographic units that provide encryption and authentication for data contained within storage media. Full interchange requires additional format specifications (such as compression algorithms and physical data format) that are beyond the scope of this standard.


IEEE Standard for Communicating Among Processors and Peripherals Using Shared Memory (Direct Memory Access - DMA)


IEEE Standard for Cryptographic Protection of Data on Block-Oriented Storage Devices

This standard specifies elements of an architecture for cryptographic protection of data on block-oriented storage devices, describing the methods, algorithms, and modes of data protection to be used.


IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink)

Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory ...


IEEE Standard for Scalable Storage Interface

This standard defines a scalable interface for use with memory-mapped storage units and other devices. The term storage unit" can encompass rotating


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Jobs related to Memory

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