Conferences related to Memory

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2018 13th IEEE Conference on Industrial Electronics and Applications (ICIEA)

Industrial Informatics, Computational Intelligence, Control and Systems, Cyber-physicalSystems, Energy and Environment, Mechatronics, Power Electronics, Signal and InformationProcessing, Network and Communication Technologies


2018 14th IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications (MESA)

The goal of the 14th ASME/IEEE MESA2018 is to bring together experts from the fields of mechatronic and embedded systems, disseminate the recent advances in the area, discuss future research directions, and exchange application experience. The main achievement of MESA2018 is to bring out and highlight the latest research results and developments in the IoT (Internet of Things) era in the field of mechatronics and embedded systems.


2018 15th IEEE International Conference on Advanced Video and Signal Based Surveillance (AVSS)

AVSS 2018 addresses underlying theory, methods, systems, and applications of video and signal based surveillance.


2018 25th IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE Signal Processing Society, is the premier forum for the presentation of technological advances and research results in the fields of theoretical, experimental, and applied image and video processing. ICIP 2018, the 25th in the series that has been held annually since 1994, brings together leading engineers and scientists in image and video processing from around the world.


2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


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Periodicals related to Memory

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Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Audio, Speech, and Language Processing, IEEE Transactions on

Speech analysis, synthesis, coding speech recognition, speaker recognition, language modeling, speech production and perception, speech enhancement. In audio, transducers, room acoustics, active sound control, human audition, analysis/synthesis/coding of music, and consumer audio. (8) (IEEE Guide for Authors) The scope for the proposed transactions includes SPEECH PROCESSING - Transmission and storage of Speech signals; speech coding; speech enhancement and noise reduction; ...


Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


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Most published Xplore authors for Memory

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Xplore Articles related to Memory

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IMCS2: Novel Device-to-Architecture Co-Design for Low-Power In-Memory Computing Platform Using Coterminous Spin Switch

[{u'author_order': 1, u'affiliation': u'Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816 USA', u'full_name': u'Farhana Parveen'}, {u'author_order': 2, u'affiliation': u'Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816 USA', u'full_name': u'Shaahin Angizi'}, {u'author_order': 3, u'affiliation': u'Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816 USA', u'full_name': u'Zhezhi He'}, {u'author_order': 4, u'affiliation': u'Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816 USA (e-mail: dfan@ucf.edu)', u'full_name': u'Deliang Fan'}] IEEE Transactions on Magnetics, None

Abstract--Spin switch (SS) is a promising spintronic device which exhibits compactness, low power, non-volatility, input-output isolation leveraging giant spin Hall effect, spin transfer torque, and dipolar coupling. In this paper, we propose a novel device-to-architecture co-design for an in-memory computing platform using coterminous SS (IMCS2), which could simultaneously work as non-volatile memory and reconfigurable in-memory logic (AND/NAND, OR/NOR, and XOR/XNOR) ...


Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications

[{u'author_order': 1, u'affiliation': u'Renesas Electronics Corporation, Kodaira, Tokyo Japan (e-mail: masanori.hayashikoshi.cj@renesas.com)', u'full_name': u'Masanori Hayashikoshi'}, {u'author_order': 2, u'affiliation': u'Renesas Electronics Corporation, Kodaira, Tokyo Japan (e-mail: hideyuki.noda.pc@renesas.com)', u'full_name': u'Hideyuki Noda'}, {u'author_order': 3, u'affiliation': u'Tokushima Bunri University, Sanuki, Kagawa Japan (e-mail: kawai@fst.bunri-u.ac.jp)', u'full_name': u'Hiroyuki Kawai'}, {u'author_order': 4, u'affiliation': u'Renesas Electronics Corporation, Kodaira, Tokyo Japan (e-mail: yasumitsu.murai.xh@renesas.com)', u'full_name': u'Yasumitsu Murai'}, {u'author_order': 5, u'affiliation': u'Renesas Electronics Corporation, Kodaira, Tokyo Japan (e-mail: sugako.otani.uj@renesas.com)', u'full_name': u'Sugako Otani'}, {u'author_order': 6, u'affiliation': u'Renesas Electronics Corporation, Kodaira, Tokyo Japan (e-mail: koji.nii.uj@renesas.com)', u'full_name': u'Koji Nii'}, {u'author_order': 7, u'affiliation': u'Graduate School of Natural Science & Technology, Kanazawa University, Kanazawa, Ishikawa Japan (e-mail: matsuda@ec.t.kanazawa-u.ac.jp)', u'full_name': u'Yoshio Matsuda'}, {u'author_order': 8, u'affiliation': u'Renesas Electronics Corporation, Kodaira, Tokyo Japan (e-mail: hiroyuki.kondo.xm@renesas.com)', u'full_name': u'Hiroyuki Kondo'}] IEEE Transactions on Multi-Scale Computing Systems, None

The low-power multi-sensor system with power management and nonvolatile memory access control for IoT applications are proposed, which achieves almost zero standby power at the no-operation modes. A power management scheme with activity localization can reduce the number of transitions between power-on and power-off modes with rescheduling and bundling task procedures. And autonomously standby mode transition control selects the optimum ...


A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design

[{u'author_order': 1, u'affiliation': u'Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China, and also with the University of Chinese Academy of Sciences, Beijing 100049, China, and also with the Beijing Institute of Remote Sensing Equipment, Beijing 100854, China.', u'full_name': u'Yinghui Tian'}, {u'author_order': 2, u'affiliation': u'Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China, and also with the University of Chinese Academy of Sciences, Beijing 100049, China.', u'full_name': u'Yong Hei'}, {u'author_order': 3, u'affiliation': u'Beijing Institute of Remote Sensing Equipment, Beijing 100854, China.', u'full_name': u'Zhizhe Liu'}, {u'author_order': 4, u'affiliation': u'Beijing Research Institute of China Telecom Corporation, Beijing, China.', u'full_name': u'Qi Shen'}, {u'author_order': 5, u'affiliation': u'School of Information Science and Technology, Southwest Jiaotong University, Chengdu, China.', u'full_name': u'Zhixiong Di'}, {u'author_order': 6, u'affiliation': u'Beijing Institute of Remote Sensing Equipment, Beijing 100854, China.', u'full_name': u'Tao Chen'}] IEEE Transactions on Circuits and Systems II: Express Briefs, None

This brief presents a modified radix-4 Fast Fourier Transform (FFT) signal flow graph, whose input and output both are in natural order. Compared with the conventional radix-4 signal flow graph, it does not buffer the result of the last stage or execute the bit-reverse operation to generate the result, but generates the result directly in the last stage. Thus, the ...


Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability

[{u'author_order': 1, u'affiliation': u'School of Computing, Creating Technologies and Engineering, Leeds Beckett University, Leeds LS6 3QS, U.K. (e-mail: M.D.Marino@leedsbeckett.ac.uk).', u'full_name': u'Mario Donato Marino'}] IEEE Transactions on Very Large Scale Integration (VLSI) Systems, None

Despite power boundaries, Moore's law is still present via scaling the number of cores, which keeps adding demands for more memory bandwidth (MBW) requested by these cores. To obtain higher MBW levels, it is fundamental to address memory controller (MC) scalability. However, MC scalability growth is limited by I/O pin counts scaling. To underline MC and pin scaling, a radio ...


Visuospatial and verbal memory differences between selected male and female adolescents of the STEM strand

[{u'author_order': 1, u'affiliation': u'La Salle Green Hills', u'full_name': u'Jan Uriel A. Marcelo'}, {u'author_order': 2, u'affiliation': u'La Salle Green Hills', u'full_name': u'Aryan Arora'}] 2018 IEEE Integrated STEM Education Conference (ISEC), None

The project began with the researchers trying to see how each gender assimilates learning based on visuospatial and verbal memory of selected Science, Technology, Engineering and Mathematics (STEM) adolescents. The project was based from other studies as well as Bem's Gender Schema Theory. The participants included in this project were from the ages of 16-19 years old in Grades 11 ...


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Educational Resources on Memory

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eLearning

No eLearning Articles are currently tagged "Memory"

IEEE.tv Videos

IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
High-Bandwidth Memory Interface Design
The Memory of Cars Talk by Tom Coughlin
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
IEEE Medal of Honor Recipient (2009): Dr. Robert Dennard
Accelerating Machine Learning with Non-Volatile Memory: Exploring device and circuit tradeoffs - Pritish Narayanan: 2016 International Conference on Rebooting Computing
Spin Dynamics in Inhomogeneously Magnetized Systems - Teruo Ono: IEEE Magnetics Society Distinguished Lecture 2016
Raspberry Pi High Speed SerDes Characterization Platform
IMS 2014: Dr. Rudolph Henning Memorial
Array storing and retrieval
Robotics History: Narratives and Networks Oral Histories: Barbara Hayes Roth
Rajiv V. Joshi - 2018 Daniel E. Noble Award for Emerging Technologies at IEEE ISSCC
2015 IEEE Honors: IEEE Richard W. Hamming Medal - Imre Csiszar
Neural Cognitive Robot: Learning, Memory and Intelligence
Jaynie Shorb from Broadcom at WIE ILC 2016
Rebooting Computing Panel - Stan Williams: 2016 Technology Time Machine
35 Years of Magnetic Heterostructures
Digital Neuromorphic Design of a Liquid State Machine for Real-Time Processing - Nicholas Soures: 2016 International Conference on Rebooting Computing

IEEE-USA E-Books

  • Supporting and Exploiting Spatial Memory in User Interfaces

    Spatial memory is an important facet of human cognition - it allows users to learn the locations of items over time and retrieve them with little effort. In human-computer interfaces, a strong knowledge of the spatial location of controls can enable a user to interact fluidly and efficiently, without needing to visually search for relevant controls. Computer interfaces should therefore be designed to provide support for developing the user's spatial memory, and they should allow the user to exploit it for rapid interaction whenever possible. However, existing systems offer varying support for spatial memory. Many modern interfaces break the user's ability to remember spatial locations, by moving or re-arranging items; others leave spatial memory underutilised, requiring slow sequences of mechanical actions to select items rather than exploiting users' strong ability to index items and controls by their on-screen locations. Supporting and Exploiting Spatial Memory in User Interfaces highlights the importance of designing for spatial memory in HCI. It summarizes empirical results on spatial memory from both the psychology and HCI domains, identifying a set of observable properties of spatial memory that can be used to inform design. It also analyses existing interfaces in the HCI literature that support or disrupt spatial memory, including space-multiplexed displays for command and navigation interfaces, different techniques for dealing with large spatial data sets, and the effects of spatial distortion. Supporting and Exploiting Spatial Memory in User Interfaces provides strong evidence that spatial knowledge of controls and data enables rapid interaction and information retrieval, and allows users to focus more of their cognitive resources on the task at hand, rather than on the interface. It is aimed at user interface designers, as well as other HCI researchers interested in spatial memory. Useful guidelines for designers are identified throughout the book, whi h provide clear advice on how and when to design with spatial memory in mind. Similarly, the concluding summary of the area, as well as methodological cautions and directions for future research provide an excellent resource for scientists interested in the importance of spatial memory in user interfaces.

  • Algorithms and Data Structures for External Memory

    Data sets in large applications are often too massive to fit completely inside the computer's internal memory. The resulting input/output communication (or I/O) between fast internal memory and slower external memory (such as disks) can be a major performance bottleneck. Algorithms and Data Structures for External Memory surveys the state of the art in the design and analysis of external memory (or EM) algorithms and data structures, where the goal is to exploit locality in order to reduce the I/O costs. A variety of EM paradigms are considered for solving batched and online problems efficiently in external memory. Algorithms and Data Structures for External Memory describes several useful paradigms for the design and implementation of efficient EM algorithms and data structures. The problem domains considered include sorting, permuting, FFT, scientific computing, computational geometry, graphs, databases, geographic information systems, and text and string processing. Algorithms and Data Structures for External Memory is an invaluable reference for anybody interested in, or conducting research in the design, analysis, and implementation of algorithms and data structures.

  • Main Memory Database Systems

    None

  • Architectural and Operating System Support for Virtual Memory

    <p>This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not only state-of- the-art virtual memory hardware and software support available today, but also emerging research trends in this space. The span of topics covers processor microarchitecture, memory systems, operating system design, and memory allocation. We show how efficient virtual memory implementations hinge on careful hardware and software cooperation, and we discuss new research directions aimed at addressing emerging problems in this space.</p> <p>Virtual memory is a classic computer science abstraction and one of the pillars of the computing revolution. It has long enabled hardware flexibility, software portability, and overall better security, to name just a few of its powerful benefits. Nearly all user-level programs today take for granted that they will have been freed from the burden of physical memory management by the hardware, the operating system, device drivers, and system libraries.</p> <p>However, despite its ubiquity in systems ranging from warehouse-scale datacenters to embedded Internet of Things (IoT) devices, the overheads of virtual memory are becoming a critical performance bottleneck today. Virtual memory architectures designed for individual CPUs or even individual cores are in many cases struggling to scale up and scale out to today's systems which now increasingly include exotic hardware accelerators (such as GPUs, FPGAs, or DSPs) and emerging memory technologies (such as non-volatile memory), and which run increasingly intensive workloads (such as virtualized and/or "big data" applications). As such, many of the fundamental abstractions and implementation approaches for virtual memory are being augmented, extended, or entirely rebuilt in order to ensure that virtual memory remains v able and performant in the years to come.</p>

  • Memory Management

    This chapter contains sections titled: Overview Strategies for Allocating Variables to Memory Design Patterns for Limited Memory Memory Management in Mobile Java Symbian OS Memory Management Summary Exercises

  • Chipless RFID Temperature Memory and Multiparameter Sensor

    This chapter presents a chipless radio‐frequency identification (RFID) memory sensor and multiparameter sensor development in two phases. It first discusses the theory of temperature threshold detection and memory material characteristics. The chapter then presents design of a single electric inductive‐capacitive (ELC) resonator loaded with memory material. Next, detailed experimentation is carried out for a highly compact chipless RFID memory sensor. Multiple parameter sensing enables a single chipless tag with a distinct ID to sense a number of physical parameters independently. Experimentation on humidity sensing and temperature threshold violation was performed in two steps. In the first step, humidity variation before temperature threshold violation was investigated. In the second step, humidity sensing is examined after the temperature exceeded the threshold. Finally, the chapter discusses the effect of temperature and humidity on each smart material to explain the lower sensitivity of polyvinyl alcohol (PVA) in high temperature conditions.

  • Community Memory: The First Public-Access Social Media System

    The first publicly available social media system, which opened in 1973 near the UC Berkeley campus, surprised its creators with the breadth of creative uses to which it was put by the users. Accessed through walk-up Teletype terminals on a mainframe time-sharing system, the Community Memory system was free, let users enter their own information and search commands directly, and relied on users' imagination to define indexing words and make searches.

  • Memory Machine Myth: The Memex, Media Archaeology, and Repertoires of Archiving

    This chapter contains sections titled: The Internet Is Not a Memory Machine, Origins of the Memory Machine Myth, The Memory Machine Myth after Bush, Warnings of the Digital Dark Age, The Wayback Machine: The Real Memex?, Techno-Volunteerism, Repertoires of Digital Archiving, Repertoires and Scripts in New Media Studies, Affordances Need Performances

  • Print Fans versus Net Fans: Women&#39;s Cultural Memory at the Threshold of New Media

    This chapter contains sections titled: Women's Anxiety about Digital Archives, "Half-digital, half-not", Bionic Women or the Borg?, The Failings of Net Fandom, Missing Female Bodies, The Cultural Imaginary of Cyberdystopianism, The Female Body Always Remains, Fan Cultural Memory as Repertoire, The Body + the Book, Uncertain Surrogacy, The Other Cyborg

  • Beyond MRAM: Nonvolatile Logic¿¿¿in¿¿¿Memory VLSI

    _The combination of spintronic devices with semiconductor integrated circuits will enable the replacement of conventional dynamic random¿¿¿access memory (DRAM) with spin¿¿¿transfer torque magnetic random¿¿¿access memory (STT¿¿¿MRAM) and facilitate high¿¿¿performance, low¿¿¿power, large¿¿¿scale¿¿¿integrated (LSI) logic circuits. Logic¿¿¿in¿¿¿memory architectures can take advantage of complementary metal¿¿¿oxide¿¿¿semiconductor/magnetic tunnel junction hybrid technology. The principles and benefits expected from these innovative architectures are explained and illustrated by several types of circuits that have been successfully designed, built, and tested. The benefits of low¿¿¿power, high¿¿¿performance, nonvolatile, spintronics¿¿¿based logic LSIs discussed in this chapter could trigger a revolutionary change in our information¿¿¿ and communication¿¿¿based society_.



Standards related to Memory

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IEEE Standard for Authenticated Encryption with Length Expansion for Storage Devices

This standard specifies requirements for cryptographic units that provide encryption and authentication for data contained within storage media. Full interchange requires additional format specifications (such as compression algorithms and physical data format) that are beyond the scope of this standard.


IEEE Standard for Communicating Among Processors and Peripherals Using Shared Memory (Direct Memory Access - DMA)


IEEE Standard for Cryptographic Protection of Data on Block-Oriented Storage Devices

This standard specifies elements of an architecture for cryptographic protection of data on block-oriented storage devices, describing the methods, algorithms, and modes of data protection to be used.


IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink)

Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory ...


IEEE Standard for Scalable Storage Interface

This standard defines a scalable interface for use with memory-mapped storage units and other devices. The term storage unit" can encompass rotating


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