Conferences related to Memory

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2018 IEEE Symposium on VLSI Circuits

Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2020 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2016 IEEE Symposium on VLSI Circuits

    circuit design to address challenges of deeply scaled technologies - e.g. dfm, variability, reliability - digital circuit techniques - analog and mixed signal circuits such as data converters and amp

  • 2014 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2012 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation

  • 2011 Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2010 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2009 Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies

  • 2008 IEEE Symposium on VLSI Circuits

  • 2007 IEEE Symposium on VLSI Circuits


2018 IEEE Symposium on VLSI Technology

New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2020 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2016 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2014 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2012 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2011 Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2010 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2009 IEEE Symposium on VLSI Technology

    - New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D-system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices

  • 2008 IEEE Symposium on VLSI Technology

  • 2007 IEEE Symposium on VLSI Technology

  • 2006 IEEE Symposium on VLSI Technology


2017 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

  • 2021 IEEE International Electron Devices Meeting (IEDM)

    the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

  • 2019 IEEE International Electron Devices Meeting (IEDM)

    the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

  • 2015 IEEE International Electron Devices Meeting (IEDM)

    the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart-power technologies, etc.

  • 2014 IEEE International Electron Devices Meeting (IEDM)

    IEDM is the world s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.

  • 2013 IEEE International Electron Devices Meeting (IEDM)

    IEDM is the world s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.

  • 2012 IEEE International Electron Devices Meeting (IEDM)

  • 2011 IEEE International Electron Devices Meeting (IEDM)

    CMOS Devices Technology, Characterization, Reliability and Yield, Displays, sensors and displays, memory technology, modeling and simulation, process technology, solid state and nanoelectronic devices.

  • 2010 IEEE International Electron Devices Meeting (IEDM)

  • 2009 IEEE International Electron Devices Meeting (IEDM)

    CMOS Devices Technology, Characterization, REliability and Yield, Displays, sensors and displays, memory technology, modeling and simulation, process technology, solid state and nanoelectronic devices

  • 2008 IEEE International Electron Devices Meeting (IEDM)

    Over the last 53 years, the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart-power technologies, etc.

  • 2007 IEEE International Electron Devices Meeting (IEDM)

  • 2006 IEEE International Electron Devices Meeting (IEDM)


2017 IEEE International Solid- State Circuits Conference - (ISSCC)

The International Solid-State Circuits Conference is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS IC's.


2015 IEEE International Reliability Physics Symposium (IRPS)

Sharing information related to cause, effects and solutions in the deign and manufacture of electronics and related components


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Periodicals related to Memory

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Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


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Xplore Articles related to Memory

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A Multi-Solver Scheme Based on Combined Field Integral Equations for Electromagnetic Modeling of Highly Complex Objects

Jian Guan; Su Yan; Jian-Ming Jin IEEE Transactions on Antennas and Propagation, 2017

A combined field integral equation (CFIE)-based multisolver scheme is presented for electromagnetic modeling of objects with complex structures and materials. In this scheme, an object is decomposed into multiple bodies based on its material property and geometry. To model bodies with complicated materials, the finite element-boundary integral (FE-BI) method is applied. To model bodies with homogeneous or conducting materials, the ...


How to Successfully Overcome Inflection Points, or Long Live Moore's Law

Paolo A. Gargini Computing in Science & Engineering, 2017

The combination of Moore's law and Dennard's scaling laws constituted the fundamental guidelines that provided the semiconductor industry with the foundation of a technically and economically viable roadmap until the end of the previous century. During this time, the transistor evolved from bipolar to PMOS to NMOS to CMOS. However, by the mid-1990s it was clear that fundamental physical limits ...


Novel solid-state imaging devices with inherent MNOS memory gate

H. Yamasaki; T. Ando IEEE Transactions on Electron Devices, 1985

A novel solid-state imaging device with an inherent MNOS memory gate is proposed and writing and reading characteristics are discussed. To improve the writing of the low light inputs, a bias charge in addition to the signal charge is transferred into the MNOS memory Capacitor from a photodiode. Both enhanced writing and a Wide dynamic range are obtained under the ...


Garbage collector assisted memory offloading for memory-constrained devices

D. Chen; A. Messer; D. Milojicic; Sandhya Dwarkadas 2003 Proceedings Fifth IEEE Workshop on Mobile Computing Systems and Applications, 2003

Our everyday lives are becoming increasingly filled with mobile devices of varying capabilities. The common practice of creating multiple versions of the same application to cope with diverse device resource capabilities increases software development and maintenance costs. We discuss an offloading method to mask out the memory constraints on devices running a typical Java virtual machine. The method allows the ...


Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design

M. Natsui; A. Tamakoshi; A. Mochizuki; H. Koike; H. Ohno; T. Endoh; T. Hanyu 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016

A new VLSI CAD environment considering stochastic behavior of MTJ devices is proposed for the evaluation of not only the performance but also the reliability of MTJ/MOS-hybrid logic LSI. The proposed simulator allows users to support the design of MTJ/MOS-hybrid LSI by RTL/gate-level hardware description, whose simulation considering stochastic switching behavior of MTJ device can be done by analog-mixed-signal simulation ...


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Educational Resources on Memory

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eLearning

A Multi-Solver Scheme Based on Combined Field Integral Equations for Electromagnetic Modeling of Highly Complex Objects

Jian Guan; Su Yan; Jian-Ming Jin IEEE Transactions on Antennas and Propagation, 2017

A combined field integral equation (CFIE)-based multisolver scheme is presented for electromagnetic modeling of objects with complex structures and materials. In this scheme, an object is decomposed into multiple bodies based on its material property and geometry. To model bodies with complicated materials, the finite element-boundary integral (FE-BI) method is applied. To model bodies with homogeneous or conducting materials, the ...


How to Successfully Overcome Inflection Points, or Long Live Moore's Law

Paolo A. Gargini Computing in Science & Engineering, 2017

The combination of Moore's law and Dennard's scaling laws constituted the fundamental guidelines that provided the semiconductor industry with the foundation of a technically and economically viable roadmap until the end of the previous century. During this time, the transistor evolved from bipolar to PMOS to NMOS to CMOS. However, by the mid-1990s it was clear that fundamental physical limits ...


Novel solid-state imaging devices with inherent MNOS memory gate

H. Yamasaki; T. Ando IEEE Transactions on Electron Devices, 1985

A novel solid-state imaging device with an inherent MNOS memory gate is proposed and writing and reading characteristics are discussed. To improve the writing of the low light inputs, a bias charge in addition to the signal charge is transferred into the MNOS memory Capacitor from a photodiode. Both enhanced writing and a Wide dynamic range are obtained under the ...


Garbage collector assisted memory offloading for memory-constrained devices

D. Chen; A. Messer; D. Milojicic; Sandhya Dwarkadas 2003 Proceedings Fifth IEEE Workshop on Mobile Computing Systems and Applications, 2003

Our everyday lives are becoming increasingly filled with mobile devices of varying capabilities. The common practice of creating multiple versions of the same application to cope with diverse device resource capabilities increases software development and maintenance costs. We discuss an offloading method to mask out the memory constraints on devices running a typical Java virtual machine. The method allows the ...


Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design

M. Natsui; A. Tamakoshi; A. Mochizuki; H. Koike; H. Ohno; T. Endoh; T. Hanyu 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016

A new VLSI CAD environment considering stochastic behavior of MTJ devices is proposed for the evaluation of not only the performance but also the reliability of MTJ/MOS-hybrid logic LSI. The proposed simulator allows users to support the design of MTJ/MOS-hybrid LSI by RTL/gate-level hardware description, whose simulation considering stochastic switching behavior of MTJ device can be done by analog-mixed-signal simulation ...


More eLearning Resources

IEEE.tv Videos

IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
The Memory of Cars Talk by Tom Coughlin
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
IEEE Medal of Honor Recipient (2009): Dr. Robert Dennard
Accelerating Machine Learning with Non-Volatile Memory: Exploring device and circuit tradeoffs - Pritish Narayanan: 2016 International Conference on Rebooting Computing
Spin Dynamics in Inhomogeneously Magnetized Systems - Teruo Ono: IEEE Magnetics Society Distinguished Lecture 2016
IMS 2014: Dr. Rudolph Henning Memorial
Robotics History: Narratives and Networks Oral Histories: Barbara Hayes Roth
Array storing and retrieval
Neural Cognitive Robot: Learning, Memory and Intelligence
Jaynie Shorb from Broadcom at WIE ILC 2016
2015 IEEE Honors: IEEE Richard W. Hamming Medal - Imre Csiszar
Rebooting Computing Panel - Stan Williams: 2016 Technology Time Machine
35 Years of Magnetic Heterostructures
Digital Neuromorphic Design of a Liquid State Machine for Real-Time Processing - Nicholas Soures: 2016 International Conference on Rebooting Computing
IEEE @ SXSW 2015 - DIY Brain Hacking: Electroceuticals & You
Brooklyn 5G Summit 2014: Unleashing Millimeter-Wave Frequency by Andreas Roessler
MicroApps: Memory Effect Enhancements for X-Parameter Models in ADS (Agilent Technologies)
Magnetic Nanowires: Revolutionizing Hard Drives, RAM, and Cancer Treatment

IEEE-USA E-Books

  • The Human Brain: Metaphor Maker

    This chapter contains sections titled: General Introduction to Brain Structure and function, Form and Function: Brain and Mind, Some Structural Elements: Brain Cells, Butterfl ies of the Soul, Some Functional Elements: Electrochemical Current and Communication among Neurons, Cellular Mechanisms for Memory Storage, Basic Organization of the Brain's Functional Regions, Techniques for Analyzing Brain Activity, Acquisition of Functional Capacities in the Brain, Some Notes on the Evolution of the Brain, Summary

  • The Human Mind: Metaphor of the World

    This chapter contains sections titled: Mind-Brain Duality, Emergent Complexity, Three Levels of Abstraction and Two Operational Spaces, Proprioception, Perception and Knowledge, Memory and Learning, The Magical Number Seven (Plus or Minus Two), Attention, Thought, Decision Making and Problem Solving, Language, Emotions, Consciousness and Qualia, Intelligence, Born or Made? Genetics or Learning, Summary

  • Evolving Memory: Logical Tasks for Cellular Automata

    We present novel experiments in the evolution of Cellular Automata (CA) to solve nontrivial tasks. Using a genetic algorithm, we evolved CA rules that can solve non-trivial logical tasks related to the density task (or majority classification problem) commonly used in the literature. We present the particle catalogs of the new rules following the computational mechanics framework. We know from Crutchfield et al (2002) that particle computation in CA is a process of information processing and integration. Here, we discuss the type of memory that emerges from the evolving CA experiments for storing and manipulating information. In particular, we contrast this type of evolved memory with the type of memory we are familiar with in Computer Science, and also with the type of biological memory instantiated by DNA. A novel CA rule obtained from our own experiments is used to elucidate the type of memory that one-dimensional CA can attain.

  • Information Theory

    This chapter contains sections titled: Issues in Information Theory Additive White Gaussian Noise Channel Information of a Source Average Information of Discrete Memoryless Sources Source Coding for a Discrete Memoryless Source Average Information of Discrete Sources Exhibiting Memory Examples Generating Model Sources Run-Length Coding for Discrete Sources Exhibiting Memory Information Transmission via Discrete Channels Capacity of Discrete Channel Shannon's Channel Coding Theorem[19,27] Capacity of Continuous Channel[16,22] Shannon's Message and Its Implications for Wireless Channels Summary and Conclusions

  • Memory Design for Testability and Fault Tolerance

    This chapter contains sections titled: General Design for Testability Techniques RAM Built-In Self-Test (BIST) Embedded Memory DFT and BIST Techniques Advanced BIST and Built-In Self-Repair Architectures DFT and BIST for ROMs Memory Error-Detection and Correction Techniques Memory Fault-Tolerance Designs This chapter contains sections titled: References

  • Beyond physical grounding and naive time: investigations into short-term memory for autonomous agents

    In this paper we present some experiments coinparing different connectionist dynamic memory models in an interactive context, including a novel version of a second-order architecture, along with an extended discussion of some foundational issues to s'hich they relate. The scenario is a fine-grained simulation of a sensor-based, non-holonomic mobile robot moving in a two dimensional environment in which are set paradigmatic short-term memory experiments involving delayed response tasks for the robotic subject. We set out our position initially in relation to symbolic AI. connectionism and nouvelle AI. In particular. we argue that despite its practical successes, the last named approach does not escape from a foundational error that in different guises undermines the programmatic aspirations of all three. We suggest that this representational problem is inherent in the implementational granularity of systems such as the subsumption architecture and argue for the notion of embedding in time, as a first step around the impasse.

  • Semiconductor Memory Reliability

    This chapter contains sections titled: General Reliability Issues RAM Failure Modes and Mechanisms Nonvolatile Memory Reliability Reliability Modeling and Failure Rate Prediction Design for Reliability Reliability Test Structures Reliability Screening and Qualification This chapter contains sections titled: References

  • The Desert of the Unreal: Democracy and Military-Funded Videogames and Simulations

    This chapter contains sections titled: The Tactical Iraqi Case Study, The Virtual Iraq Case Study, The Palace of Memory, Identity in Play, Trust and Face, Critical Play, Testing the Prototypes: Gamer Culture and Primary Reception, Backlash in the Professional Game Development Community, Language Games in Tactical Iraqi, Res Publica: Videogames and the Material Culture of Civic Life

  • Electric Power Generation as Cloud Infrastructure Analog

    Production of electric power via thermal power plants is very mature while production of virtual compute, memory, storage, and networking resources to serve applications via cloud infrastructure is still rapidly evolving. There are fundamental similarities between these two apparently different businesses that afford useful insights into how the infrastructure service provider operational practices are likely to mature. This chapter considers parallels and useful insights between electric power generation via thermal generating systems and cloud computing infrastructure. It also discusses several insightful similarities between electricity market and grid operations and cloud infrastructure. The power industry has sophisticated notions of capacity ratings, locational considerations, service curtailment, and demand management which have applicability to cloud computing. The power industry actively balances electricity generation with demand across time and space via sophisticated unit commitment and economic dispatch systems, processes and policies, including day-ahead commitment plans, and 5 minute load following economic dispatch.

  • References

    In development for thirty years, Soar is a general cognitive architecture that integrates knowledge-intensive reasoning, reactive execution, hierarchical reasoning, planning, and learning from experience, with the goal of creating a general computational system that has the same cognitive abilities as humans. In contrast, most AI systems are designed to solve only one type of problem, such as playing chess, searching the Internet, or scheduling aircraft departures. Soar is both a software system for agent development and a theory of what computational structures are necessary to support human-level agents. Over the years, both software system and theory have evolved. This book offers the definitive presentation of Soar from theoretical and practical perspectives, providing comprehensive descriptions of fundamental aspects and new components. The current version of Soar features major extensions, adding reinforcement learning, semantic memory, episodic memory, mental imagery, and an appraisal-based model of emotion. This book describes details of Soar's component memories and processes and offers demonstrations of individual components, components working in combination, and real-world applications. Beyond these functional considerations, the book also proposes requirements for general cognitive architectures and explicitly evaluates how well Soar meets those requirements.



Standards related to Memory

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IEEE Standard for Authenticated Encryption with Length Expansion for Storage Devices

This standard specifies requirements for cryptographic units that provide encryption and authentication for data contained within storage media. Full interchange requires additional format specifications (such as compression algorithms and physical data format) that are beyond the scope of this standard.


IEEE Standard for Communicating Among Processors and Peripherals Using Shared Memory (Direct Memory Access - DMA)


IEEE Standard for Cryptographic Protection of Data on Block-Oriented Storage Devices

This standard specifies elements of an architecture for cryptographic protection of data on block-oriented storage devices, describing the methods, algorithms, and modes of data protection to be used.


IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink)

Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory ...


IEEE Standard for Scalable Storage Interface

This standard defines a scalable interface for use with memory-mapped storage units and other devices. The term storage unit" can encompass rotating


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