Conferences related to Annealing

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2013 14th International Conference on Ultimate Integration on Silicon (ULIS)

The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2012 13th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2011 12th International Conference on Ultimate Integration on Silicon (ULIS)

    ULIS is an annual conference that regroups the European research community working on advanced silicon devices and nanodevices. It has been held annually since 2000. The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2009 10th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.


2012 10th IEEE International Conference on Semiconductor Electronics (ICSE)

For the last twenty years, ICSE has become the preeminent international forum on semiconductor electronics embracing all aspects of the semiconductor technology from circuit device, modeling and simulation, photonics and sensor technology, MEMs technology, process and fabrication, packaging technology and manufacturing, failure analysis and reliability, material and devices and nanoelectronics.

  • 2010 IEEE International Conference on Semiconductor Electronics (ICSE)

    Application of microelectronics in product development; Device modeling, simulation and design; Device packaging & testing; Device physics and characterization; Material and new fabrication facilities technologies; Micromachining, microsensors and MEMS; Microwave device and MMIC; Opto-electronics and photonics technology; Process technology (CMOS,bipolar,BiCMOS,GaAs, etc); Reliability and failure analysis; Training and human resource development in microelectronics industry; Wafer Fabrication facilities and

  • 2008 IEEE International Conference on Semiconductor Electronics (ICSE)

    ICSE2008 continues a series of biennial conferences that began in 1992 in Kuala Lumpur. This conference embraces all aspects of semiconductor technology and is aimed at bringing together scientists, engineers and researchers from industry and academia to gather and explore various issues and trends in the related field.

  • 2006 IEEE International Conference on Semiconductor Electronics (ICSE)


2010 18th International Conference on Advanced Thermal Processing of Semiconductors (RTP)

Thermal processing of semiconductors



Periodicals related to Annealing

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Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Nuclear Science, IEEE Transactions on

All aspects of the theory and applications of nuclear science and engineering, including instrumentation for the detection and measurement of ionizing radiation; particle accelerators and their controls; nuclear medicine and its application; effects of radiation on materials, components, and systems; reactor instrumentation and controls; and measurement of radiation in space.



Most published Xplore authors for Annealing

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Xplore Articles related to Annealing

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Information-Oriented Models and Methods for Construction Project Supply Chain Coordination

Xiaolong Xue; Chengshuang Sun 2009 Fourth International Conference on Computer Sciences and Convergence Information Technology, 2009

This work focuses on establishing coordination models and method with different information in the operation process of established construction project supply chains (CPSCs). A two-level programming model for collaborative decision making is established to find optimal solutions for all stakeholders in CPSCs. An agent-based negotiation framework for CPSCs coordination in dynamic decision environment is designed based on the intelligent agent ...


Initial Version of State Transition Algorithm

Xiaojun Zhou; Chunhua Yang; Weihua Gui 2011 Second International Conference on Digital Manufacturing & Automation, 2011

In terms of the concepts of state and state transition, a new algorithm-State Transition Algorithm (STA) is proposed in order to probe into classical and intelligent optimization algorithms. On the basis of state and state transition, it becomes much simpler and easier to understand. As for continuous function optimization problems, three special operators named rotation, translation and expansion are presented. ...


A new floorplan simultaneously placing blocks over two logic layers for sea-of-gate gate arrays

1993 IEEE International Symposium on Circuits and Systems, 1993

First Page of the Article ![](/xploreAssets/images/absImages/00693009.png)


An algorithm for hierarchical floorplan design

D. F. Wong; K. -S. The 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 1989

A floorplan design algorithm is presented which is based on the following: (1) a new representation of order-5 hierarchical floorplan by normalized 2-5 Polish expressions; (2) a novel neighborhood structure defined by a set of four moves that bring a solution to its neighboring solutions; (3) an efficient floorplan area optimization algorithm for general hierarchical floorplans that makes the cost ...


Comparisons of the performance on transient chaotic neural network with different output functions

Qian Li; Liang Sun Fifth World Congress on Intelligent Control and Automation (IEEE Cat. No.04EX788), 2004

Based on the chaotic simulated annealing network used by Chen & Aihara, which has better searching properties than traditional Hopfield-Tank neural network, we proposed other two different output functions and applied all of them to 4 city TSP respectively. We constructed continuous, discrete and continuous- discrete neural networks, introduced a basic principle to initialize parameter. At last, we analyzed the ...


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Educational Resources on Annealing

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eLearning

Information-Oriented Models and Methods for Construction Project Supply Chain Coordination

Xiaolong Xue; Chengshuang Sun 2009 Fourth International Conference on Computer Sciences and Convergence Information Technology, 2009

This work focuses on establishing coordination models and method with different information in the operation process of established construction project supply chains (CPSCs). A two-level programming model for collaborative decision making is established to find optimal solutions for all stakeholders in CPSCs. An agent-based negotiation framework for CPSCs coordination in dynamic decision environment is designed based on the intelligent agent ...


Initial Version of State Transition Algorithm

Xiaojun Zhou; Chunhua Yang; Weihua Gui 2011 Second International Conference on Digital Manufacturing & Automation, 2011

In terms of the concepts of state and state transition, a new algorithm-State Transition Algorithm (STA) is proposed in order to probe into classical and intelligent optimization algorithms. On the basis of state and state transition, it becomes much simpler and easier to understand. As for continuous function optimization problems, three special operators named rotation, translation and expansion are presented. ...


A new floorplan simultaneously placing blocks over two logic layers for sea-of-gate gate arrays

1993 IEEE International Symposium on Circuits and Systems, 1993

First Page of the Article ![](/xploreAssets/images/absImages/00693009.png)


An algorithm for hierarchical floorplan design

D. F. Wong; K. -S. The 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 1989

A floorplan design algorithm is presented which is based on the following: (1) a new representation of order-5 hierarchical floorplan by normalized 2-5 Polish expressions; (2) a novel neighborhood structure defined by a set of four moves that bring a solution to its neighboring solutions; (3) an efficient floorplan area optimization algorithm for general hierarchical floorplans that makes the cost ...


Comparisons of the performance on transient chaotic neural network with different output functions

Qian Li; Liang Sun Fifth World Congress on Intelligent Control and Automation (IEEE Cat. No.04EX788), 2004

Based on the chaotic simulated annealing network used by Chen & Aihara, which has better searching properties than traditional Hopfield-Tank neural network, we proposed other two different output functions and applied all of them to 4 city TSP respectively. We constructed continuous, discrete and continuous- discrete neural networks, introduced a basic principle to initialize parameter. At last, we analyzed the ...


More eLearning Resources

IEEE.tv Videos

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IEEE-USA E-Books

  • Fundamentals of Simulated Annealing

    This chapter contains sections titled: Introduction Basic Principles Cooling Schedule SA Algorithm for the Traveling Salesman Problem SA for Transmission Network Expansion Problem Parallel Simulated Annealing Applications of Simulated Annealing Conclusions References

  • About the Author

    The ever-growing number of new telecommunications technologies, along with the rapid growth of data networks and cable television systems has created a demand for sound network planning. In one concise volume, this book offers professionals in telecommunications and networking and graduate students an introduction to the theory underlying the interdisciplinary field of network planning, a critical aspect of network management that integrates planning telecommunications and data networks. In PLANNING TELECOMMUNICATIONS NETWORKS you will learn about the mathematical theory behind network planning, including an accessible treatment of linear programming and graph algorithms. Other featured topics cover: Reliability theory for network planning Recent software advances in databases, expert systems, object-oriented programming, data mining and data visualization Latest developments in new optimization techniques such as tabu search, simulated annealing, genetic algorithms, and neural networks Complete with homework problems, this text offers you a broad overview of network planning to begin your exploration of this emerging field. Sponsored by: IEEE Communications Society. An Instructor's Manual presenting detailed solutions to all the problems in the book is available upon request from the Wiley Makerting Department.

  • Software and Optimization for Planning

    This chapter contains sections titled: Introduction Object-Oriented Programming Databases Geographic Information Systems Expert Systems Nonlinear Model Optimization Tabu Search Simulated Annealing Genetic Algorithms Neural Networks Problems

  • SubstrateAware MixedSignal Macrocell Placement in WRIGHT

    We describe a set of placement algorithms for handling substrate-coupled switching noise. A typical mixed-signal IC has both sensitive analog and noisy digital circuits, and the common substrate parasitically couples digital switching transients into the sensitive analog regions of the chip. To preserve the integrity of sensitive analog signals, it is thus necessary to electrically isolate the analog and digital. We argue that optimal area utilization requires such isolation be designed into the system during first- cut chip-level placement. We present algorithms that incorporate commonly used isolation techniques within an automatic placement framework. Our substrate- noise evaluation mechanism uses a simplified substrate model and simple electrical representations for the noisy digital macrocells. The digital/analog interactions determined through these models are incorporated into a simulated annealing macrocell placement framework. Automatic placement results indicate these substrateaware algorithms allow efficient mixed-signal placement optimization.

  • Introduction to Optimization in Electromagnetics

    This chapter contains sections titled: Optimizing a Function of One Variable Optimizing a Function of Multiple Variables Comparing Local Numerical Optimization Algorithms Simulated Annealing Genetic Algorithm

  • No title

    Adiabatic quantum computation (AQC) is an alternative to the better-known gate model of quantum computation. The two models are polynomially equivalent, but otherwise quite dissimilar: one property that distinguishes AQC from the gate model is its analog nature. Quantum annealing (QA) describes a type of heuristic search algorithm that can be implemented to run in the ``native instruction set'' of an AQC platform. D-Wave Systems Inc. manufactures {quantum annealing processor chips} that exploit quantum properties to realize QA computations in hardware. The chips form the centerpiece of a novel computing platform designed to solve NP-hard optimization problems. Starting with a 16-qubit prototype announced in 2007, the company has launched and sold increasingly larger models: the 128-qubit D-Wave One system was announced in 2010 and the 512-qubit D-Wave Two system arrived on the scene in 2013. A 1,000-qubit model is expected to be available in 2014. This monograph presents an introduc ory overview of this unusual and rapidly developing approach to computation. We start with a survey of basic principles of quantum computation and what is known about the AQC model and the QA algorithm paradigm. Next we review the D-Wave technology stack and discuss some challenges to building and using quantum computing systems at a commercial scale. The last chapter reviews some experimental efforts to understand the properties and capabilities of these unusual platforms. The discussion throughout is aimed at an audience of computer scientists with little background in quantum computation or in physics.

  • Learning capabilities of Boolean networks

    Boolean networks can learn 10 perform specific tasks. Here, some cases are described where a network is trained on a given problem, namely, a sub-set of examples of this task is provided to the system. This procedure results in a final network which is able to perform correctly on instances that differ from those in the examples, thus showing a capability to recover the general rule underlying the task. The training phase amounts to an optimization process which is carried out using simulated annealing, a search strategy derived from statistical physics. Depending on problem complexity, network size, and number of examples used in the training, different learning regimes occur. For small networks an exact analysis of the statistical mechanics of the system shows that learning takes place as a phase transition. Indeed, thermodynamical quantities related to this transition (critical temperature, specific heat) are related to the complexity of the problem. We also show that a problem can be efficiently learned when it can be implemented in many different ways, ie, generalization is an entropy effect. We also discuss a comparison between different learning schemes and optimization algorithms.

  • Systemlevel Routing of MixedSignal ASICs in WREN

    This paper presents new techniques for global and detailed routing of the macrocell-style analog core of a mixed-signal ASIC. We combine a comparatively simple geometric model of the problem with an aggressive simulated annealing formulation that selects paths while accommodating numerous signal-integrity constraints. Experimental results demonstrate that it is critical to attack such constraints both globally (system-level) and locally (channel-level) to meet designer-specified performance targets.

  • The Digital Hormone Model for Self-Organization

    This paper presents the Digital Hormone Model (DHM) as a new computational model for self-organization. The model is a generalization of an earlier distributed control system for self-reconfigurable robots [1-3] and an integration of reaction-diffusion model with stochastic cellular automata. In this model, cells secrete hormones, and hormones diffuse into space and influence the behaviors of other cells to self-organize into global patterns. In contrast to the reaction-diffusion models, cells movements are computed not by the Turing's differential equations [4] hut by stochastic rules that are based on the concentration of hormones in the neighboring space. Different from simulated annealing, the stochastic rules are not the Metropolis rule (5], which will not produce the desired results here. Experimental results have shown that the simulated cells in the DHM produce results that match to the observations made in the biological experiments where homogenous skin cells selforganize into feather buds regulated by hormones [6]. With the unique properties of being distributed, scalable, robust, and adaptive, the DHM opens opportunities for new hypotheses, theories, and experiments for further investigating the nature of self-organization

  • Synthesis of HighPerformance Analog Circuits in ASTRX/OBLX

    We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel unconstrained optimization formulation of the circuit synthesis problem. We have implemented this strategy in a pair of tools called ASTRX and OBLX. To show the generality of our new approach, we have used this system to resynthesize essentially all the analog synthesis benchmarks published in the past decade; ASTRX/OBLX has resynthesized circuits in an afternoon that, for some prior approaches, had required months. To show the viability of the approach on difficult circuits, we have resynthesized a recently published (and patented), high-performance operational amplifier; ASTRX/OBLX achieved performance comparable to the expert manual design. And finally, to test the limits of the approach on industrial-sized problems, we have synthesized the component cells of a pipelined A/D converter; ASTRX/OBLX successfully generated cells 2-3Ã? more complex than those published previously.



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