CMOSFET logic devices
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2016 IEEE Symposium on VLSI Technology
New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.
2014 IEEE International Symposium on Circuits and Systems (ISCAS)
The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems Society and the world’s premier networking forum in the highly active fields of theory, design and implementation of circuits and systems.ISCAS 2014 will have a special focus on nano/bio circuits and systems applied to enhancing living and lifestyles, and seeks to address multidisciplinary challenges in healthcare and well-being, the environment and climate change.
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Kechichian, K.; Al-Khalili, A.J.; Al-Khalili, D. Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on, 1994
In VLSI CMOS circuit design chip area, signal propagation delay and power dissipation are conflicting criteria that need to be optimized in order to improve performance. Full circuit simulation and manual optimization can be costly and time consuming. We present here a method of obtaining different circuit configurations from a given multiple-output Boolean expression. An optimum circuit is selected from ...
Yi-Ming Sheu; Sheng-Jier Yang; Chih-Chiang Wang; Chih-Sheng Chang; Li-Ping Huang; Tsung-Yi Huang; Ming-Jer Chen; Diaz, C.H. Electron Devices, IEEE Transactions on, 2005
The effect of shallow trench isolation mechanical stress on MOSFET dopant diffusion has become significant, and affects device behavior for sub-100-nm technologies. This paper presents a stress-dependent dopant diffusion model and demonstrates its capability to reflect experimental results for a state- of-the-art logic CMOS technology. The proposed stress-dependent dopant diffusion model is shown to successfully reproduce device characteristics covering a ...
Knight, T.; Wu, H.M. VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on, 1993
We have presented a novel technique that allows skew-free distribution of digital signals with known and controllable arrival times. The technique requires adjustments and measurements only at the sender. Our method is based on measuring the round trip delay of a signal and then adjusting it with a pair of matched delay lines. This technique can be modified to work ...
Togo, M.; Mogami, T.; Kubota, R.; Nobusawa, H.; Hamada, M.; Inoue, K.; Mikagi, K.; Yoshida, K.; Soda, E.; Kishi, S.; Satou, K.; Yamamoto, T.; Takeda, K.; Aimoto, Y.; Nakazawa, Y.; Toyoshima, H. Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International, 1999
We have demonstrated three key integration technologies of thermally stable dual-gate CMOSFETs for DRAM-embedded ASICs. These technologies include: (1) a thermally stable W-polycide gate for every MOSFET and CoSi/sub 2/ diffusion for logic CMOS to maintain low resistance, (2) nitrogen implantation into WSi/sub 2/ to prevent lateral dopant diffusion without gate depletion, and (3) a Si/sub 3/N/sub 4//TEOS-BPSG stacked interlayer ...
Han, L.K.; Crowder, S.; Hargrove, M.; Wu, E.; Lo, S.H.; Guarin, F.; Crabbe, E.; Su, L. Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International, 1997
We present a detailed study of electrical characteristics of sub-3 nm gate oxides grown on nitrogen implanted Si substrates (N/sub 2/ I/I oxides). The new results that advance the understanding of N/sub 2/ I/I oxides are the following: lower tunneling current, higher TDDB lifetime and reduced defect density are reported in N/sub 2/ I/I oxides for the first time. In ...
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