CMOSFET logic devices
58 resources related to CMOSFET logic devices
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2016 IEEE Symposium on VLSI Technology
New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.
2014 IEEE International Symposium on Circuits and Systems (ISCAS)
The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems Society and the world’s premier networking forum in the highly active fields of theory, design and implementation of circuits and systems.ISCAS 2014 will have a special focus on nano/bio circuits and systems applied to enhancing living and lifestyles, and seeks to address multidisciplinary challenges in healthcare and well-being, the environment and climate change.
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Michinishi, H.; Yokohira, T.; Okamoto, T.; Kobayashi, T.; Hondo, T. Test Symposium, 2003. ATS 2003. 12th Asian, 2003
We already proposed a supply current test method for detecting floating gate defects in CMOS ICs. In the method, increase of the supply current caused by defects is promoted by superposing a sinusoidal signal on the supply voltage. In this study, we propose one way to improve detectability of the method for the defects. They are detected by analyzing the ...
Staszewski, R.B.; Wallberg, J.; Jinseok Koh; Balsara, P.T. Implementation of High Performance Circuits, 2004. (DCAS-04). Proceedings of the 2004 IEEE Dallas/CAS Workshop, 2004
We present high-speed digital circuits that comprise the first ever reported all-digital 2.4 GHz frequency synthesizer and transmitter that meet the Bluetooth specifications. The chip is built in a digital 130 nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm2. The transmitter architecture is based on an all-digital phase-locked loop (AD-PLL), ...
Matsumoto, T.; Maeda, S.; Dang, H.; Uchida, T.; Ota, K.; Hirano, Y.; Sayama, H.; Iwamatsu, T.; Ipposhi, T.; Oda, H.; Maegawa, S.; Inoue, Y.; Nishimura, T. Electron Devices Meeting, 2002. IEDM '02. International, 2002
For high performance RF/analog and logic device technology, novel SOI wafer engineering featuring <100>-channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from <110> to <100>. Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (f/sub max/) for NMOSFET is improved ...
Chuan-Yu Wang; Roy, K. Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on, 1997
Maximum instantaneous power in VLSI circuits has a great impact on circuit reliability and the design of power and ground lines. To synthesize highly reliable systems, accurate estimates of maximum power must be obtained in various design phases. Unfortunately, determining the input patterns to induce the maximum current (power) is essentially a combinatorial optimization problem. Even for circuits with small ...
Joshi, R.V.; Yee, F.; Kim, K.; Williams, R.Q.; Chuang, C.T. SOI Conference, IEEE International 2002, 2002
Summary form only given. We have presented a VT-wave-pipeline technique for pseudo-static circuit style. The technique was evaluated using the critical path of a 64 bit carry-look-ahead adder in a 1.2 V, 0.13 μm PD/SOI technology. A performance improvement of 11.5% was obtained without significantly increasing the standby or active power. The technique was also shown to reduce the history ...
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