Conferences related to CMOSFET logic devices

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2017 IEEE 17th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

Silicon-based devices, passives, integrated circuits, and applications for high frequency systems.


2017 IEEE International Reliability Physics Symposium (IRPS)

Study of reliability as applied to semiconductor manufacturing, automotive, PV, and other engineering disciplines. International participation.


2017 IEEE International Symposium on Circuits and Systems (ISCAS)

TBA


2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

This industry-wide event gathers together widely known experts, contributed papers and invited talks focused on SOI Technology, Low-Voltage Devices/Circuits/Architectures, and 3D Integration.


2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

•Low power CMOS and embedded memory •Foundry technology •RF process, device and integration technology •Standalone memory: DRAM, FLASH, emerging memory technology •Advanced process modules: e.g. gate stack, junction, strain/channel engineering, low-R contact, low-C spacer/ILD, interconnect technology, ALE and selective deposition, etc.•Nanopatterning: Multiple patterning, Directed Self-Assembly, EUV, etc. •Power and analog IC device and technology •Advanced CMOS process and devices: Ge, SiGe, III-V, FinFET, GAA, 2D materials/1D nanowires •Material, Process and device modeling •TFT and organic electronics •MEMS, imagers and sensors •Advanced manufacturing technology, metrology and yield •Reliability physics, characterization and test •Advanced packaging and 2.5D/3D Integration•Photonics and Beyond CMOS Technology •Energy harvesting technology •Wearable and loE enabling technologies


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Periodicals related to CMOSFET logic devices

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Microwave Theory and Techniques, IEEE Transactions on

Microwave theory, techniques, and applications as they relate to components, devices, circuits, and systems involving the generation, transmission, and detection of microwaves.


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.



Most published Xplore authors for CMOSFET logic devices

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Xplore Articles related to CMOSFET logic devices

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New protection structure against minority carrier injection

M. Zitouni; E. de Fresart; R. De Souza; X. Lin; J. Morrison; P. Parris 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440), 2003

In this paper, a simple and effective protection structure against minority carrier injection is proposed. The structure consists of an Nwell between the power device and the CMOS associated with a PBL (P buried layer) and an NBL (N buried layer) underneath the CMOS logic. The efficiency of this technique was evaluated in 2D and 3D device simulation.


High-density 16/8/4-bit configurable multiplier

A. Bermak; D. Martinez; J. -L. Noullet IEE Proceedings - Circuits, Devices and Systems, 1997

A configurable serial-parallel multiplier based on Braun's and Baugh-Wooley's algorithms is presented. The multiplier can be configured to perform either signed or unsigned multiplications and to achieve variable precision. In this device one factor A(m) is fed serially with an arbitrary wordlength m while the other B(n) is stored in parallel with a configurable number of bits n=4, 8 or ...


Search for optimum and scalable COSMOS

S. Kaya; A. Al-Ahmadi 2004 Abstracts 10th International Workshop on Computational Electronics, 2004

This present work reports the result of 3D simulations aimed at optimizing structural parameters for tuning symmetric operation of COSMOS, improving leakage and switching performance. In addition, we also investigate the scalability of COSMOS structure as a function of lateral and vertical device dimensions. Thus we will show how significant area gains can be obtained in static CMOS logic circuits, ...


High performance low power V/sub T/-wave-pipeline CMOS circuit in PD/SOI technology

Joshi; Yee; Kim; Williams; Chuang 2002 IEEE International SOI Conference, 2002

Summary form only given. We have presented a V/sub T/-wave-pipeline technique for pseudo-static circuit style. The technique was evaluated using the critical path of a 64 bit carry-look-ahead adder in a 1.2 V, 0.13 /spl mu/m PD/SOI technology. A performance improvement of 11.5% was obtained without significantly increasing the standby or active power. The technique was also shown to reduce ...


A BIST circuit for I<sub>DDQ</sub> tests

M. Hashizume; T. Takeda; H. Yotsuyanagi; T. Tamesada; Y. Miura; K. Kinoshita 2003 Test Symposium, 2003

In this paper, an IDDQ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for IDDQ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that IDDQ test time can ...


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Educational Resources on CMOSFET logic devices

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eLearning

New protection structure against minority carrier injection

M. Zitouni; E. de Fresart; R. De Souza; X. Lin; J. Morrison; P. Parris 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440), 2003

In this paper, a simple and effective protection structure against minority carrier injection is proposed. The structure consists of an Nwell between the power device and the CMOS associated with a PBL (P buried layer) and an NBL (N buried layer) underneath the CMOS logic. The efficiency of this technique was evaluated in 2D and 3D device simulation.


High-density 16/8/4-bit configurable multiplier

A. Bermak; D. Martinez; J. -L. Noullet IEE Proceedings - Circuits, Devices and Systems, 1997

A configurable serial-parallel multiplier based on Braun's and Baugh-Wooley's algorithms is presented. The multiplier can be configured to perform either signed or unsigned multiplications and to achieve variable precision. In this device one factor A(m) is fed serially with an arbitrary wordlength m while the other B(n) is stored in parallel with a configurable number of bits n=4, 8 or ...


Search for optimum and scalable COSMOS

S. Kaya; A. Al-Ahmadi 2004 Abstracts 10th International Workshop on Computational Electronics, 2004

This present work reports the result of 3D simulations aimed at optimizing structural parameters for tuning symmetric operation of COSMOS, improving leakage and switching performance. In addition, we also investigate the scalability of COSMOS structure as a function of lateral and vertical device dimensions. Thus we will show how significant area gains can be obtained in static CMOS logic circuits, ...


High performance low power V/sub T/-wave-pipeline CMOS circuit in PD/SOI technology

Joshi; Yee; Kim; Williams; Chuang 2002 IEEE International SOI Conference, 2002

Summary form only given. We have presented a V/sub T/-wave-pipeline technique for pseudo-static circuit style. The technique was evaluated using the critical path of a 64 bit carry-look-ahead adder in a 1.2 V, 0.13 /spl mu/m PD/SOI technology. A performance improvement of 11.5% was obtained without significantly increasing the standby or active power. The technique was also shown to reduce ...


A BIST circuit for I<sub>DDQ</sub> tests

M. Hashizume; T. Takeda; H. Yotsuyanagi; T. Tamesada; Y. Miura; K. Kinoshita 2003 Test Symposium, 2003

In this paper, an IDDQ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for IDDQ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that IDDQ test time can ...


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Standards related to CMOSFET logic devices

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Jobs related to CMOSFET logic devices

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