IEEE Organizations related to CMOSFET logic devices

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Conferences related to CMOSFET logic devices

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2018 IEEE Symposium on VLSI Technology

New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2020 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2016 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2014 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2012 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2011 Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2010 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2009 IEEE Symposium on VLSI Technology

    - New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D-system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices

  • 2008 IEEE Symposium on VLSI Technology


2014 IEEE International Symposium on Circuits and Systems (ISCAS)

The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems Society and the world’s premier networking forum in the highly active fields of theory, design and implementation of circuits and systems.ISCAS 2014 will have a special focus on nano/bio circuits and systems applied to enhancing living and lifestyles, and seeks to address multidisciplinary challenges in healthcare and well-being, the environment and climate change.

  • 2013 IEEE International Symposium on Circuits and Systems (ISCAS)

    The Symposium will focus on circuits and systems employing nanodevices (both extremely scaled CMOS and non-CMOS devices) and circuit fabrics (mixture of standard CMOS and evolving nano-structure elements) and their implementation cost, switching speed, energy efficiency, and reliability. The ISCAS 2010 will include oral and poster sessions; tutorials given by experts in state-of-the-art topics; and special sessions, with the aim of complementing the regular program with topics of particular interest to the community that cut across and beyond disciplines traditionally represented at ISCAS.

  • 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012

    2012 International Symposium on Circuits and Systems (ISCAS 2012) aims at providing the world's premier forum of leading researchers in circuits and systems areas from academia and industries, especially focusing on Convergence of BINET (BioInfoNanoEnviro Tech.) which represents IT, NT and ET and leading Human Life Revolutions. Prospective authors are invited to submit papers of their original works emphasizing contributions beyond the present state of the art. We also welcome proposals on special tuto

  • 2011 IEEE International Symposium on Circuits and Systems (ISCAS)

    The IEEE International Symposium on Circuits and Systems (ISCAS) is the world's premier networking forum of leading researchers in the highly active fields of theory, design and implementation of circuits and systems.

  • 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010

    ISCAS is a unique conference dealing with circuits and systems. It's the yearly "rendez-vous" of leading researchers, coming both from academia and industry, in the highly active fields of theory, design and implementation of circuits and systems. The Symposium will focus on circuits and systems for high quality life and consumer technologies, including mobile communications, advanced multimedia systems, sensor networks and Nano-Bio Circuit Fabrics and Systems.

  • 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009

    Analog Signal Processing, Biomedical Circuits and Systems, Blind Signal Processing, Cellular Neural Networks and Array Computing, Circuits and Systems for Communications, Computer-Aided Network Design, Digital Signal Processing, Life-Science Systems and Applications, Multimedia Systems and Applications, Nanoelectronics and Gigascale Systems, Neural Systems and Applications, Nonlinear Circuits and Applications, Power Systems and Power Electronic Circuits, Sensory Systems, Visual Signal Processing and Communi

  • 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008

  • 2007 IEEE International Symposium on Circuits and Systems - ISCAS 2007

  • 2006 IEEE International Symposium on Circuits and Systems - ISCAS 2006

  • 2005 IEEE International Symposium on Circuits and Systems - ISCAS 2005



Periodicals related to CMOSFET logic devices

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.



Most published Xplore authors for CMOSFET logic devices

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Xplore Articles related to CMOSFET logic devices

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Anomalous history behavior in stacked PD SOI gates

M. B. Ketchen; M. Bhushan 2003 IEEE International Conference on SOI, 2003

In this article described a new experiment with multiple input stacked gates in which delays can be over 7% outside the 1SW/2SW range. This result, which is not predicted by models, is thought to be either a floating body SOI effect or related to traps in the gate oxide and would be present in bulk as well.


Library-less synthesis for static CMOS combinational logic circuits

S. Gavrilov; A. Glebov; S. Pullela; S. C. Moore; A. Dharchoudhury; R. Panda; G. Vijayan; D. T. Blaauw 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1997

Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. ...


Search for optimum and scalable COSMOS

S. Kaya; A. Al-Ahmadi 2004 Abstracts 10th International Workshop on Computational Electronics, 2004

This present work reports the result of 3D simulations aimed at optimizing structural parameters for tuning symmetric operation of COSMOS, improving leakage and switching performance. In addition, we also investigate the scalability of COSMOS structure as a function of lateral and vertical device dimensions. Thus we will show how significant area gains can be obtained in static CMOS logic circuits, ...


Electrical characteristics and reliability of sub-3 nm gate oxides grown on nitrogen implanted silicon substrates

L. K. Han; S. Crowder; M. Hargrove; E. Wu; S. H. Lo; F. Guarin; E. Crabbe; L. Su International Electron Devices Meeting. IEDM Technical Digest, 1997

We present a detailed study of electrical characteristics of sub-3 nm gate oxides grown on nitrogen implanted Si substrates (N/sub 2/ I/I oxides). The new results that advance the understanding of N/sub 2/ I/I oxides are the following: lower tunneling current, higher TDDB lifetime and reduced defect density are reported in N/sub 2/ I/I oxides for the first time. In ...


Average leakage current macromodeling for dual-threshold voltage circuits

Yongjun Xu; Zuying Luo; Zhiguo Chen; Xlaowei Li 2003 Test Symposium, 2003

Dual threshold voltage design is the most effective technique for reducing leakage current of integrated circuits. In this paper, we put forward an average leakage current macromodeling for dual-threshold circuits and propose two methods to conquer it, table-lookup based simulation and statistical analysis. The simulation is an efficient general-purposed method for leakage current estimation. For stochastic input circuits, a new ...


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Educational Resources on CMOSFET logic devices

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eLearning

Anomalous history behavior in stacked PD SOI gates

M. B. Ketchen; M. Bhushan 2003 IEEE International Conference on SOI, 2003

In this article described a new experiment with multiple input stacked gates in which delays can be over 7% outside the 1SW/2SW range. This result, which is not predicted by models, is thought to be either a floating body SOI effect or related to traps in the gate oxide and would be present in bulk as well.


Library-less synthesis for static CMOS combinational logic circuits

S. Gavrilov; A. Glebov; S. Pullela; S. C. Moore; A. Dharchoudhury; R. Panda; G. Vijayan; D. T. Blaauw 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1997

Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. ...


Search for optimum and scalable COSMOS

S. Kaya; A. Al-Ahmadi 2004 Abstracts 10th International Workshop on Computational Electronics, 2004

This present work reports the result of 3D simulations aimed at optimizing structural parameters for tuning symmetric operation of COSMOS, improving leakage and switching performance. In addition, we also investigate the scalability of COSMOS structure as a function of lateral and vertical device dimensions. Thus we will show how significant area gains can be obtained in static CMOS logic circuits, ...


Electrical characteristics and reliability of sub-3 nm gate oxides grown on nitrogen implanted silicon substrates

L. K. Han; S. Crowder; M. Hargrove; E. Wu; S. H. Lo; F. Guarin; E. Crabbe; L. Su International Electron Devices Meeting. IEDM Technical Digest, 1997

We present a detailed study of electrical characteristics of sub-3 nm gate oxides grown on nitrogen implanted Si substrates (N/sub 2/ I/I oxides). The new results that advance the understanding of N/sub 2/ I/I oxides are the following: lower tunneling current, higher TDDB lifetime and reduced defect density are reported in N/sub 2/ I/I oxides for the first time. In ...


Average leakage current macromodeling for dual-threshold voltage circuits

Yongjun Xu; Zuying Luo; Zhiguo Chen; Xlaowei Li 2003 Test Symposium, 2003

Dual threshold voltage design is the most effective technique for reducing leakage current of integrated circuits. In this paper, we put forward an average leakage current macromodeling for dual-threshold circuits and propose two methods to conquer it, table-lookup based simulation and statistical analysis. The simulation is an efficient general-purposed method for leakage current estimation. For stochastic input circuits, a new ...


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IEEE-USA E-Books

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Standards related to CMOSFET logic devices

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No standards are currently tagged "CMOSFET logic devices"


Jobs related to CMOSFET logic devices

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