CMOSFET logic devices
58 resources related to CMOSFET logic devices
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2016 IEEE Symposium on VLSI Technology
New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.
2014 IEEE International Symposium on Circuits and Systems (ISCAS)
The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems Society and the world’s premier networking forum in the highly active fields of theory, design and implementation of circuits and systems.ISCAS 2014 will have a special focus on nano/bio circuits and systems applied to enhancing living and lifestyles, and seeks to address multidisciplinary challenges in healthcare and well-being, the environment and climate change.
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Kechichian, K.; Al-Khalili, A.J.; Al-Khalili, D. Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on, 1994
In VLSI CMOS circuit design chip area, signal propagation delay and power dissipation are conflicting criteria that need to be optimized in order to improve performance. Full circuit simulation and manual optimization can be costly and time consuming. We present here a method of obtaining different circuit configurations from a given multiple-output Boolean expression. An optimum circuit is selected from ...
Matsumoto, T.; Maeda, S.; Dang, H.; Uchida, T.; Ota, K.; Hirano, Y.; Sayama, H.; Iwamatsu, T.; Ipposhi, T.; Oda, H.; Maegawa, S.; Inoue, Y.; Nishimura, T. Electron Devices Meeting, 2002. IEDM '02. International, 2002
For high performance RF/analog and logic device technology, novel SOI wafer engineering featuring <100>-channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from <110> to <100>. Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (f/sub max/) for NMOSFET is improved ...
Ketchen, M.B.; Bhushan, M. SOI Conference, 2003. IEEE International, 2003
In this article described a new experiment with multiple input stacked gates in which delays can be over 7% outside the 1SW/2SW range. This result, which is not predicted by models, is thought to be either a floating body SOI effect or related to traps in the gate oxide and would be present in bulk as well.
Kaya, S.; Al-Ahmadi, A. Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on, 2004
This present work reports the result of 3D simulations aimed at optimizing structural parameters for tuning symmetric operation of COSMOS, improving leakage and switching performance. In addition, we also investigate the scalability of COSMOS structure as a function of lateral and vertical device dimensions. Thus we will show how significant area gains can be obtained in static CMOS logic circuits, ...
Han, L.K.; Crowder, S.; Hargrove, M.; Wu, E.; Lo, S.H.; Guarin, F.; Crabbe, E.; Su, L. Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International, 1997
We present a detailed study of electrical characteristics of sub-3 nm gate oxides grown on nitrogen implanted Si substrates (N/sub 2/ I/I oxides). The new results that advance the understanding of N/sub 2/ I/I oxides are the following: lower tunneling current, higher TDDB lifetime and reduced defect density are reported in N/sub 2/ I/I oxides for the first time. In ...
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