IEEE Organizations related to CMOSFET logic devices

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Conferences related to CMOSFET logic devices

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2016 IEEE Symposium on VLSI Technology

New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2020 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2018 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2014 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2012 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2011 Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2010 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2009 IEEE Symposium on VLSI Technology

    - New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D-system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices

  • 2008 IEEE Symposium on VLSI Technology


2014 IEEE International Symposium on Circuits and Systems (ISCAS)

The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems Society and the world’s premier networking forum in the highly active fields of theory, design and implementation of circuits and systems.ISCAS 2014 will have a special focus on nano/bio circuits and systems applied to enhancing living and lifestyles, and seeks to address multidisciplinary challenges in healthcare and well-being, the environment and climate change.

  • 2013 IEEE International Symposium on Circuits and Systems (ISCAS)

    The Symposium will focus on circuits and systems employing nanodevices (both extremely scaled CMOS and non-CMOS devices) and circuit fabrics (mixture of standard CMOS and evolving nano-structure elements) and their implementation cost, switching speed, energy efficiency, and reliability. The ISCAS 2010 will include oral and poster sessions; tutorials given by experts in state-of-the-art topics; and special sessions, with the aim of complementing the regular program with topics of particular interest to the community that cut across and beyond disciplines traditionally represented at ISCAS.

  • 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012

    2012 International Symposium on Circuits and Systems (ISCAS 2012) aims at providing the world's premier forum of leading researchers in circuits and systems areas from academia and industries, especially focusing on Convergence of BINET (BioInfoNanoEnviro Tech.) which represents IT, NT and ET and leading Human Life Revolutions. Prospective authors are invited to submit papers of their original works emphasizing contributions beyond the present state of the art. We also welcome proposals on special tuto

  • 2011 IEEE International Symposium on Circuits and Systems (ISCAS)

    The IEEE International Symposium on Circuits and Systems (ISCAS) is the world's premier networking forum of leading researchers in the highly active fields of theory, design and implementation of circuits and systems.

  • 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010

    ISCAS is a unique conference dealing with circuits and systems. It's the yearly "rendez-vous" of leading researchers, coming both from academia and industry, in the highly active fields of theory, design and implementation of circuits and systems. The Symposium will focus on circuits and systems for high quality life and consumer technologies, including mobile communications, advanced multimedia systems, sensor networks and Nano-Bio Circuit Fabrics and Systems.

  • 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009

    Analog Signal Processing, Biomedical Circuits and Systems, Blind Signal Processing, Cellular Neural Networks and Array Computing, Circuits and Systems for Communications, Computer-Aided Network Design, Digital Signal Processing, Life-Science Systems and Applications, Multimedia Systems and Applications, Nanoelectronics and Gigascale Systems, Neural Systems and Applications, Nonlinear Circuits and Applications, Power Systems and Power Electronic Circuits, Sensory Systems, Visual Signal Processing and Communi

  • 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008

  • 2007 IEEE International Symposium on Circuits and Systems - ISCAS 2007

  • 2006 IEEE International Symposium on Circuits and Systems - ISCAS 2006

  • 2005 IEEE International Symposium on Circuits and Systems - ISCAS 2005



Periodicals related to CMOSFET logic devices

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.



Most published Xplore authors for CMOSFET logic devices

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Xplore Articles related to CMOSFET logic devices

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New protection structure against minority carrier injection

M. Zitouni; E. de Fresart; R. De Souza; X. Lin; J. Morrison; P. Parris Bipolar/BiCMOS Circuits and Technology Meeting, 2003. Proceedings of the, 2003

In this paper, a simple and effective protection structure against minority carrier injection is proposed. The structure consists of an Nwell between the power device and the CMOS associated with a PBL (P buried layer) and an NBL (N buried layer) underneath the CMOS logic. The efficiency of this technique was evaluated in 2D and 3D device simulation.


Library-less synthesis for static CMOS combinational logic circuits

S. Gavrilov; A. Glebov; S. Pullela; S. C. Moore; A. Dharchoudhury; R. Panda; G. Vijayan; D. T. Blaauw Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on, 1997

Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. ...


LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load

S. Mitra; A. Salman; D. P. Ioannou; D. E. Ioannou SOI Conference, IEEE International 2002, 2002

Summary form only given. Over the last several years there has been a great deal of excitement about the double-gate (DG) SOI MOSFET as the enabling Si device for the 0.05 μm node and beyond. As a result a number of DG structures have been proposed and analyzed, and several have been experimentally demonstrated. Although these devices are currently being ...


Search for optimum and scalable COSMOS

S. Kaya; A. Al-Ahmadi Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on, 2004

This present work reports the result of 3D simulations aimed at optimizing structural parameters for tuning symmetric operation of COSMOS, improving leakage and switching performance. In addition, we also investigate the scalability of COSMOS structure as a function of lateral and vertical device dimensions. Thus we will show how significant area gains can be obtained in static CMOS logic circuits, ...


Loading effects on metastable parameters of CMOS latches

C. L. Portmann; T. H. Y. Meng VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on, 1993

We have discussed the behavior of buffered and unbuffered latches versus loading from a metastable performance viewpoint. A formula to determine T/sub 0/ for a buffered latch from an unbuffered one has been described. Measured results were presented for buffered and unbuffered latches. The results shown here are relevant to standard cell or gate array ASIC designers who generally use ...


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Educational Resources on CMOSFET logic devices

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eLearning

New protection structure against minority carrier injection

M. Zitouni; E. de Fresart; R. De Souza; X. Lin; J. Morrison; P. Parris Bipolar/BiCMOS Circuits and Technology Meeting, 2003. Proceedings of the, 2003

In this paper, a simple and effective protection structure against minority carrier injection is proposed. The structure consists of an Nwell between the power device and the CMOS associated with a PBL (P buried layer) and an NBL (N buried layer) underneath the CMOS logic. The efficiency of this technique was evaluated in 2D and 3D device simulation.


Library-less synthesis for static CMOS combinational logic circuits

S. Gavrilov; A. Glebov; S. Pullela; S. C. Moore; A. Dharchoudhury; R. Panda; G. Vijayan; D. T. Blaauw Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on, 1997

Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. ...


LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load

S. Mitra; A. Salman; D. P. Ioannou; D. E. Ioannou SOI Conference, IEEE International 2002, 2002

Summary form only given. Over the last several years there has been a great deal of excitement about the double-gate (DG) SOI MOSFET as the enabling Si device for the 0.05 μm node and beyond. As a result a number of DG structures have been proposed and analyzed, and several have been experimentally demonstrated. Although these devices are currently being ...


Search for optimum and scalable COSMOS

S. Kaya; A. Al-Ahmadi Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on, 2004

This present work reports the result of 3D simulations aimed at optimizing structural parameters for tuning symmetric operation of COSMOS, improving leakage and switching performance. In addition, we also investigate the scalability of COSMOS structure as a function of lateral and vertical device dimensions. Thus we will show how significant area gains can be obtained in static CMOS logic circuits, ...


Loading effects on metastable parameters of CMOS latches

C. L. Portmann; T. H. Y. Meng VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on, 1993

We have discussed the behavior of buffered and unbuffered latches versus loading from a metastable performance viewpoint. A formula to determine T/sub 0/ for a buffered latch from an unbuffered one has been described. Measured results were presented for buffered and unbuffered latches. The results shown here are relevant to standard cell or gate array ASIC designers who generally use ...


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Standards related to CMOSFET logic devices

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Jobs related to CMOSFET logic devices

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