Conferences related to CMOSFET logic devices

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2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAM

  • 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

    Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAMs22. Phase Change Memory23. 3-Dimensional Memory24. MEMS Technology25. Thin Film Transistors26. Biosensors27. PV and Energy Harvesting28. Front End of Line (FEOL) R

  • 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT)

    Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAMs22. Phase Change Memory23. 3-Dimensional Memory24. MEMS Technology25. Thin Film Transistors26. Biosensors27. PV and Energy Harvesting28. Front End of Line (FEOL) R

  • 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

    Silicon IC, Silicon/germanium devices , Interconnect , Low K and High Kdielectric , Advance Memories , nano -electronics, Organic and Compound semiconductor devices ,sensors and MEMS, Semiconductor material erization, Reliability , Modeling and simulation,Packaging and testing , Digital, Analog, Mixed Signal IC and SOC design technology,Low -power, RF devices & circuits, ICCAD

  • 2010 IEEE 10th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

    Silicon IC, Silicon/germanium devices , Interconnect , Low K and High K dielectric , Advance Memories , nano-electronics, Organic and Compound semiconductor devices , sensors and MEMS, Semiconductor material characterization, Reliability , Modeling and simulation, Packaging and testing , Digital, Analog, Mixed Signal IC and SOC design technology,Low-power, RF devices & circuits, IC CAD .

  • 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT)

  • 2006 8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT)

  • 2004 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT)


2018 IEEE 18th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

This is a set of five conferences with a focus on wireless components, applications and systems that affect both now and our future lifestyle. The main niche of these conferences is to bring together technologists, circuit designers, system designers and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be benchmarked against the needs of circuit designers at the bleeding edge of RF systems. This is also an area where today's design compromises can trigger tomorrow's advanced technologies, where dreams can become a reality.


2018 IEEE 8th International Nanoelectronics Conferences (INEC)

IEEE-INEC 2018 is the 8th in a series of very successful conferences initiated by Nanotech Chapter of IEEE Singapore Section. It provides an international forum for the presentation and discussion of recent advances in the areas of Nanoelectronics, Nanodevices, Nanosystems and IoT.


2018 IEEE International Reliability Physics Symposium (IRPS)

Reliability issues associated with semiconductors, foundries, IoT and other areas


2018 IEEE International Symposium on Circuits and Systems (ISCAS)

ISCAS is the world’s premier networking and exchange forum for leading researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS is the flagship conference of the IEEE Circuits and Systems Society and aim to bring together its multidisciplinary community that has a strong history of cultivating creative, proof-of-concept research in a diverse range of technical domains including analog and digital circuits and systems, nanotechnology, sensors, nonlinear systems, biosystems, neural systems, signal processing, and communications.


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Periodicals related to CMOSFET logic devices

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Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


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Xplore Articles related to CMOSFET logic devices

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High performance low power V/sub T/-wave-pipeline CMOS circuit in PD/SOI technology

[{u'author_order': 1, u'affiliation': u'IBM Res. Div., IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA', u'full_name': u'Joshi'}, {u'author_order': 2, u'affiliation': u'IBM Res. Div., IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA', u'full_name': u'Yee'}, {u'author_order': 3, u'affiliation': u'IBM Res. Div., IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA', u'full_name': u'Kim'}, {u'author_order': 4, u'full_name': u'Williams'}, {u'author_order': 5, u'full_name': u'Chuang'}] 2002 IEEE International SOI Conference, None

Summary form only given. We have presented a V/sub T/-wave-pipeline technique for pseudo-static circuit style. The technique was evaluated using the critical path of a 64 bit carry-look-ahead adder in a 1.2 V, 0.13 /spl mu/m PD/SOI technology. A performance improvement of 11.5% was obtained without significantly increasing the standby or active power. The technique was also shown to reduce ...


New protection structure against minority carrier injection

[{u'author_order': 1, u'affiliation': u'SmartMOS Technol. Center, Motorola, Tempe, AZ, USA', u'full_name': u'M. Zitouni'}, {u'author_order': 2, u'affiliation': u'SmartMOS Technol. Center, Motorola, Tempe, AZ, USA', u'full_name': u'E. de Fresart'}, {u'author_order': 3, u'affiliation': u'SmartMOS Technol. Center, Motorola, Tempe, AZ, USA', u'full_name': u'R. De Souza'}, {u'author_order': 4, u'affiliation': u'SmartMOS Technol. Center, Motorola, Tempe, AZ, USA', u'full_name': u'X. Lin'}, {u'author_order': 5, u'affiliation': u'SmartMOS Technol. Center, Motorola, Tempe, AZ, USA', u'full_name': u'J. Morrison'}, {u'author_order': 6, u'affiliation': u'SmartMOS Technol. Center, Motorola, Tempe, AZ, USA', u'full_name': u'P. Parris'}] 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440), None

In this paper, a simple and effective protection structure against minority carrier injection is proposed. The structure consists of an Nwell between the power device and the CMOS associated with a PBL (P buried layer) and an NBL (N buried layer) underneath the CMOS logic. The efficiency of this technique was evaluated in 2D and 3D device simulation.


EOS/ESD analysis of high-density logic chips

[{u'author_order': 1, u'affiliation': u'Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA', u'full_name': u'S. Ramaswamy'}, {u'author_order': 2, u'full_name': u'C. Duvvury'}, {u'author_order': 3, u'full_name': u'A. Amerasekera'}, {u'author_order': 4, u'full_name': u'V. Reddy'}, {u'author_order': 5, u'full_name': u'S. M. Kang'}] 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium, None

Electrical overstress (EOS) and electrostatic discharge (ESD) are a major cause for field failures in integrated circuits. Effective design of I/O protection circuits is important to achieve overall EOS/ESD reliability. A wide range of CMOS applications is leading to IC chips with different on-chip capacitance values. Using experimental methods combined with device/circuit simulators, we show the important role of chip ...


Optimizing CMOS combinatorial circuits using multiple attribute decision making techniques

[{u'author_order': 1, u'affiliation': u'Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada', u'full_name': u'K. Kechichian'}, {u'author_order': 2, u'full_name': u'A. J. Al-Khalili'}, {u'author_order': 3, u'full_name': u'D. Al-Khalili'}] 1994 Proceedings of Canadian Conference on Electrical and Computer Engineering, None

In VLSI CMOS circuit design chip area, signal propagation delay and power dissipation are conflicting criteria that need to be optimized in order to improve performance. Full circuit simulation and manual optimization can be costly and time consuming. We present here a method of obtaining different circuit configurations from a given multiple-output Boolean expression. An optimum circuit is selected from ...


Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs

[{u'author_order': 1, u'affiliation': u'Dept. of Adv. Device Technol., Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan', u'full_name': u'Yi-Ming Sheu'}, {u'author_order': 2, u'affiliation': u'Dept. of Adv. Device Technol., Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan', u'full_name': u'Sheng-Jier Yang'}, {u'author_order': 3, u'affiliation': u'Dept. of Adv. Device Technol., Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan', u'full_name': u'Chih-Chiang Wang'}, {u'author_order': 4, u'affiliation': u'Dept. of Adv. Device Technol., Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan', u'full_name': u'Chih-Sheng Chang'}, {u'author_order': 5, u'affiliation': u'Dept. of Adv. Device Technol., Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan', u'full_name': u'Li-Ping Huang'}, {u'author_order': 6, u'affiliation': u'Dept. of Adv. Device Technol., Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan', u'full_name': u'Tsung-Yi Huang'}, {u'author_order': 7, u'full_name': u'Ming-Jer Chen'}, {u'author_order': 8, u'full_name': u'C. H. Diaz'}] IEEE Transactions on Electron Devices, 2005

The effect of shallow trench isolation mechanical stress on MOSFET dopant diffusion has become significant, and affects device behavior for sub-100-nm technologies. This paper presents a stress-dependent dopant diffusion model and demonstrates its capability to reflect experimental results for a state- of-the-art logic CMOS technology. The proposed stress-dependent dopant diffusion model is shown to successfully reproduce device characteristics covering a ...


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Educational Resources on CMOSFET logic devices

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eLearning

No eLearning Articles are currently tagged "CMOSFET logic devices"

IEEE.tv Videos

FinSAL: A Novel FinFET Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices - Himanshu Thapliyal: 2016 International Conference on Rebooting Computing
The Josephson Effect: Josephson Digital Electronics in the Soviet Union
Dynamic Logic Example
A perspective shift from Fuzzy logic to Neutrosophic Logic - Swati Aggarwal
35 Years of Magnetic Heterostructures
BSIM Spice Model Enables FinFET and UTB IC Design
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
The Hertzsprung-Russell Diagram: Introduction to Fuzzy Logic
Superconductive Energy-Efficient Computing - ASC-2014 Plenary-series - 6 of 13 - Wednesday 2014/8/13
Perpendicular magnetic anisotropy: From ultralow power spintronics to cancer therapy
CIRCUIT DESIGN USING FINFETS
The Sorites Paradox: Introduction to Fuzzy Logic
Hamid R Tizhoosh - Fuzzy Image Processing
2013 IEEE Robert N. Noyce Medal
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
Provably-Correct Robot Control with LTLMoP, OMPL and ROS
Low-energy High-performance Computing based on Superconducting Technology
Plastic Logic's QUE E-Reader is Best of CES
IMS 2011 Microapps - Volume Manufacturing Trends for Automotive Radar Devices
Analog Devices SP4T RF MEMS Switch with Integrated Driver Circuitry for RF Instrumentation: MicroApps 2015 - Analog Devices

IEEE-USA E-Books

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Standards related to CMOSFET logic devices

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IEEE Guide for the Application of Faulted Circuit Indicators for 200 / 600 A, Three-phase Underground Distribution

This application guide provides information on what a FCI is designed to do and describes methods for selecting FCIs for three-phase, 200 / 600 amp underground distribution circuits. This application guide will complement the existing single phase application guide.



Jobs related to CMOSFET logic devices

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