Conferences related to CMOSFET logic devices

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2014 IEEE International Symposium on Circuits and Systems (ISCAS)

The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems Society and the world s premier networking forum in the highly active fields of theory, design and implementation of circuits and systems. ISCAS 2014 will have a special focus on nano/bio circuits and systems applied to enhancing living and lifestyles, and seeks to address multidisciplinary challenges in healthcare and well-being, the environment and climate change.


2014 IEEE Symposium on VLSI Technology

New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2020 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2018 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2016 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2013 Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, RF, Analog, Mixed-Signal, High-Voltage, Imager, and MEMS. - Advanced gate stacks and interconnects in VLSI processes and devices - Advanced lithography and fine-patterning technologies for high-density VLSI - New functional devices beyond CMOS with a path for VLSI implementation - Packing of VLSI devices including 3D-system integration - Advanced device analysis, materials and modeling for VLSIs - Reliability related

  • 2012 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2011 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2010 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2009 Symposium on VLSI Technology

    - New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D-system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices

  • 2008 IEEE Symposium on VLSI Technology



Xplore Articles related to CMOSFET logic devices

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Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs

Morifuji, E.; Yoshida, T.; Kanda, M.; Matsuda, S.; Yamada, S.; Matsuoka, F. Electron Devices, IEEE Transactions on , 2006

The authors show new guidelines for Vdd and threshold voltage (Vth) scaling for both the logic blocks and the high-density SRAM cells from low power- dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum Vdd is very sensitive to switching activity in addition to ...


Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications

Matsumoto, T.; Maeda, S.; Dang, H.; Uchida, T.; Ota, K.; Hirano, Y.; Sayama, H.; Iwamatsu, T.; Ipposhi, T.; Oda, H.; Maegawa, S.; Inoue, Y.; Nishimura, T. Electron Devices Meeting, 2002. IEDM '02. International , 2002

For high performance RF/analog and logic device technology, novel SOI wafer engineering featuring <100>-channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from <110> to <100>. Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (f/sub max/) for NMOSFET is improved ...


LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load

Mitra, S.; Salman, A.; Ioannou, D.P.; Ioannou, D.E. SOI Conference, IEEE International 2002 , 2002

Summary form only given. Over the last several years there has been a great deal of excitement about the double-gate (DG) SOI MOSFET as the enabling Si device for the 0.05 μm node and beyond. As a result a number of DG structures have been proposed and analyzed, and several have been experimentally demonstrated. Although these devices are currently being ...


Library-less synthesis for static CMOS combinational logic circuits

Gavrilov, S.; Glebov, A.; Pullela, S.; Moore, S.C.; Dharchoudhury, A.; Panda, R.; Vijayan, G.; Blaauw, D.T. Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on , 1997

Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. ...


Full Two-Dimensional Markov Chain Analysis of Thermal Soft Errors in Subthreshold Nanoscale CMOS Devices

Jannaty, P.; Sabou, F.C.; Bahar, R.I.; Mundy, J.; Patterson, W.; Zaslavsky, A. Device and Materials Reliability, IEEE Transactions on , 2011

Thermally induced fluctuations in the logic state of a simple flip-flop occur on a timescale that renders them impossible to simulate through Monte Carlo methods. In a previous work, an analytical framework based on Markov chains and queue theory was introduced along with a symbolic solution for a truncated 1-D queue, diagonally connecting the two stable logic states in a ...


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Periodicals related to CMOSFET logic devices

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.



IEEE Organizations related to CMOSFET logic devices

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