CMOS

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Complementary metal–oxide–semiconductor (CMOS) is a technology for constructing integrated circuits. (Wikipedia.org)






Conferences related to CMOS

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2019 IEEE Energy Conversion Congress and Exposition (ECCE)

IEEE-ECCE 2019 brings together practicing engineers, researchers, entrepreneurs and other professionals for interactive and multi-disciplinary discussions on the latest advances in energy conversion technologies. The Conference provides a unique platform for promoting your organization.

  • 2018 IEEE Energy Conversion Congress and Exposition (ECCE)

    The scope of ECCE 2018 includes all technical aspects of research, design, manufacture, application and marketing of devices, components, circuits and systems related to energyconversion, industrial power and power electronics.

  • 2017 IEEE Energy Conversion Congress and Exposition (ECCE)

    ECCE is the premier global conference covering topics in energy conversion from electric machines, power electronics, drives, devices and applications both existing and emergent

  • 2016 IEEE Energy Conversion Congress and Exposition (ECCE)

    The Energy Conversion Congress and Exposition (ECCE) is focused on research and industrial advancements related to our sustainable energy future. ECCE began as a collaborative effort between two societies within the IEEE: The Power Electronics Society (PELS) and the Industrial Power Conversion Systems Department (IPCSD) of the Industry Application Society (IAS) and has grown to the premier conference to discuss next generation technologies.

  • 2015 IEEE Energy Conversion Congress and Exposition

    The scope of ECCE 2015 includes all technical aspects of research, design, manufacture, application and marketing of devices, components, circuits and systems related to energy conversion, industrial power and power electronics.

  • 2014 IEEE Energy Conversion Congress and Exposition (ECCE)

    Those companies who have an interest in selling to: research engineers, application engineers, strategists, policy makers, and innovators, anyone with an interest in energy conversion systems and components.

  • 2013 IEEE Energy Conversion Congress and Exposition (ECCE)

    The scope of the congress interests include all technical aspects of the design, manufacture, application and marketing of devices, components, circuits and systems related to energy conversion, industrial power conversion and power electronics.

  • 2012 IEEE Energy Conversion Congress and Exposition (ECCE)

    The IEEE Energy Conversion Congress and Exposition (ECCE) will be held in Raleigh, the capital of North Carolina. This will provide a forum for the exchange of information among practicing professionals in the energy conversion business. This conference will bring together users and researchers and will provide technical insight as well.

  • 2011 IEEE Energy Conversion Congress and Exposition (ECCE)

    IEEE 3rd Energy Conversion Congress and Exposition follows the inagural event held in San Jose, CA in 2009 and 2nd meeting held in Atlanta, GA in 2010 as the premier conference dedicated to all aspects of energy processing in industrial, commercial, transportation and aerospace applications. ECCE2011 has a strong empahasis on renewable energy sources and power conditioning, grid interactions, power quality, storage and reliability.

  • 2010 IEEE Energy Conversion Congress and Exposition (ECCE)

    This conference covers all areas of electrical and electromechanical energy conversion. This includes power electrics, power semiconductors, electric machines and drives, components, subsystems, and applications of energy conversion systems.

  • 2009 IEEE Energy Conversion Congress and Exposition (ECCE)

    The scope of the conference include all technical aspects of the design, manufacture, application and marketing of devices, circuits, and systems related to electrical energy conversion technology


2019 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


2019 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2019 IEEE International Ultrasonics Symposium (IUS)

The conference covers all aspects of the technology associated with ultrasound generation and detection and their applications.


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Periodicals related to CMOS

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Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


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Xplore Articles related to CMOS

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High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)

[{u'author_order': 1, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan. Phone: +81-45-776-4041, FAX: +81-45-776-4111, E-mail: sanuki@amc.toshiba.co.jp', u'authorUrl': u'https://ieeexplore.ieee.org/author/37265001600', u'full_name': u'T. Sanuki', u'id': 37265001600}, {u'author_order': 2, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37286647000', u'full_name': u'T. Iwamoto', u'id': 37286647000}, {u'author_order': 3, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37585685000', u'full_name': u'K. Ota', u'id': 37585685000}, {u'author_order': 4, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37265004800', u'full_name': u'T. Komoda', u'id': 37265004800}, {u'author_order': 5, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37711101000', u'full_name': u'H. Yamazaki', u'id': 37711101000}, {u'author_order': 6, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293752600', u'full_name': u'A. Eiho', u'id': 37293752600}, {u'author_order': 7, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/38230907800', u'full_name': u'K. Miyagi', u'id': 38230907800}, {u'author_order': 8, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37361109100', u'full_name': u'K. Nakayama', u'id': 37361109100}, {u'author_order': 9, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37706372500', u'full_name': u'O. Fuji', u'id': 37706372500}, {u'author_order': 10, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37264964900', u'full_name': u'M. Togo', u'id': 37264964900}, {u'author_order': 11, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37285220700', u'full_name': u'K. Ohno', u'id': 37285220700}, {u'author_order': 12, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37265688900', u'full_name': u'H. Yoshimura', u'id': 37265688900}, {u'author_order': 13, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37270816400', u'full_name': u'K. Yoshida', u'id': 37270816400}, {u'author_order': 14, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37275231700', u'full_name': u'T. Ito', u'id': 37275231700}, {u'author_order': 15, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37426690300', u'full_name': u'A. Mineji', u'id': 37426690300}, {u'author_order': 16, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/38239356700', u'full_name': u'K. Yoshino', u'id': 38239356700}, {u'author_order': 17, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37669210200', u'full_name': u'T. Itani', u'id': 37669210200}, {u'author_order': 18, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37268056000', u'full_name': u'K. Matsuo', u'id': 37268056000}, {u'author_order': 19, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37440076100', u'full_name': u'T. Sato', u'id': 37440076100}, {u'author_order': 20, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37325583700', u'full_name': u'S. Mori', u'id': 37325583700}, {u'author_order': 21, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37291044700', u'full_name': u'K. Nakazawa', u'id': 37291044700}, {u'author_order': 22, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37288648200', u'full_name': u'M. Nakazawa', u'id': 37288648200}, {u'author_order': 23, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293764300', u'full_name': u'T. Shinyama', u'id': 37293764300}, {u'author_order': 24, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37265270600', u'full_name': u'K. Suguro', u'id': 37265270600}, {u'author_order': 25, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37284373800', u'full_name': u'I. Mizushima', u'id': 37284373800}, {u'author_order': 26, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293767000', u'full_name': u'S. Iwasa', u'id': 37293767000}, {u'author_order': 27, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37285172800', u'full_name': u'S. Muramatsu', u'id': 37285172800}, {u'author_order': 28, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37301394100', u'full_name': u'K. Nagaoka', u'id': 37301394100}, {u'author_order': 29, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37273904000', u'full_name': u'M. Ikeda', u'id': 37273904000}, {u'author_order': 30, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37289522500', u'full_name': u'M. Saito', u'id': 37289522500}, {u'author_order': 31, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293754800', u'full_name': u'H. Naruse', u'id': 37293754800}, {u'author_order': 32, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'full_name': u'Y. Enomoto'}, {u'author_order': 33, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37315349400', u'full_name': u'T. Kitano', u'id': 37315349400}, {u'author_order': 34, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37269130900', u'full_name': u'M. Iwai', u'id': 37269130900}, {u'author_order': 35, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37275157800', u'full_name': u'K. Imai', u'id': 37275157800}, {u'author_order': 36, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37265046900', u'full_name': u'N. Nagashima', u'id': 37265046900}, {u'author_order': 37, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37286514100', u'full_name': u'T. Kuwata', u'id': 37286514100}, {u'author_order': 38, u'affiliation': u'Advanced CMOS Technology Group, Advanced Logic Technology Dept., System LSI Division, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 235-8522, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293761900', u'full_name': u'F. Matsuoka', u'id': 37293761900}] 2007 IEEE International Electron Devices Meeting, 2007

This paper describes the fabrication and performance of CMOS transistors featuring flash lamp annealing (FLA) for 45 nm node. We show, for the first time, applying FLA prior to spike RTA as S/D annealing is effective to enhance the channel stress in PFET with epitaxially grown SiGe (eSiGe) S/D. In NFET, FLA recovers the damaged layer in S/D extension caused ...


Practical implications of via-middle Cu TSV-induced stress in a 28nm CMOS technology for Wide-IO logic-memory interconnect

[{u'author_order': 1, u'affiliation': u'Texas Instruments, Advanced CMOS Group, External Development & Manufacturing, Dallas, USA', u'full_name': u'J. West'}, {u'author_order': 2, u'affiliation': u'Texas Instruments, Advanced CMOS Group, External Development & Manufacturing, Dallas, USA', u'full_name': u'Y.S. Choi'}, {u'author_order': 3, u'affiliation': u'Texas Instruments, Advanced CMOS Group, External Development & Manufacturing, Dallas, USA', u'full_name': u'C. Vartuli'}] 2012 Symposium on VLSI Technology (VLSIT), 2012

The impact of isolated and arrayed 10×60μm via-middle Cu TSVs on 8LM 28nm node CMOS poly-SiON P/NFETs was electrically measured for proximities >;4 μm at 27C and 105C. The largest observed shift in Ion(<;2.3%) is significantly less than that from other context-dependent sources such as dual stress liner boundaries (~10%). NanoBeam Diffraction measurements of Si strain within 5μm of TSVs ...


Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

[{u'author_order': 1, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation. Phone: +81-45-770-3498, FAX: +81-45-770-3194, E-mail: eiho@semicon.toshiba.co.jp', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293752600', u'full_name': u'A. Eiho', u'id': 37293752600}, {u'author_order': 2, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37265001600', u'full_name': u'T. Sanuki', u'id': 37265001600}, {u'author_order': 3, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37264993600', u'full_name': u'E. Morifuji', u'id': 37264993600}, {u'author_order': 4, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37286647000', u'full_name': u'T. Iwamoto', u'id': 37286647000}, {u'author_order': 5, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37427916100', u'full_name': u'G. Sudo', u'id': 37427916100}, {u'author_order': 6, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293746900', u'full_name': u'K. Fukasaku', u'id': 37293746900}, {u'author_order': 7, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37585685000', u'full_name': u'K. Ota', u'id': 37585685000}, {u'author_order': 8, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37710044500', u'full_name': u'T. Sawada', u'id': 37710044500}, {u'author_order': 9, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37706372500', u'full_name': u'O. Fuji', u'id': 37706372500}, {u'author_order': 10, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293730000', u'full_name': u'H. Nii', u'id': 37293730000}, {u'author_order': 11, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37264964900', u'full_name': u'M. Togo', u'id': 37264964900}, {u'author_order': 12, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37285220700', u'full_name': u'K. Ohno', u'id': 37285220700}, {u'author_order': 13, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37270816400', u'full_name': u'K. Yoshida', u'id': 37270816400}, {u'author_order': 14, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37707016000', u'full_name': u'H. Tsuda', u'id': 37707016000}, {u'author_order': 15, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37275231700', u'full_name': u'T. Ito', u'id': 37275231700}, {u'author_order': 16, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37722170500', u'full_name': u'Y. Shiozaki', u'id': 37722170500}, {u'author_order': 17, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37707648100', u'full_name': u'N. Fuji', u'id': 37707648100}, {u'author_order': 18, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37711101000', u'full_name': u'H. Yamazaki', u'id': 37711101000}, {u'author_order': 19, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37288648200', u'full_name': u'M. Nakazawa', u'id': 37288648200}, {u'author_order': 20, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293767000', u'full_name': u'S. Iwasa', u'id': 37293767000}, {u'author_order': 21, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37285172800', u'full_name': u'S. Muramatsu', u'id': 37285172800}, {u'author_order': 22, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37301394100', u'full_name': u'K. Nagaoka', u'id': 37301394100}, {u'author_order': 23, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37269130900', u'full_name': u'M. Iwai', u'id': 37269130900}, {u'author_order': 24, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37273904000', u'full_name': u'M. Ikeda', u'id': 37273904000}, {u'author_order': 25, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37289522500', u'full_name': u'M Saito', u'id': 37289522500}, {u'author_order': 26, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293754800', u'full_name': u'H. Naruse', u'id': 37293754800}, {u'author_order': 27, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293758200', u'full_name': u'Y. Enomoto', u'id': 37293758200}, {u'author_order': 28, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37706353200', u'full_name': u'Kitano', u'id': 37706353200}, {u'author_order': 29, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37273067200', u'full_name': u'S. Yamada', u'id': 37273067200}, {u'author_order': 30, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37275157800', u'full_name': u'K. Imai', u'id': 37275157800}, {u'author_order': 31, u'affiliation': u'Sony Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37265046900', u'full_name': u'N. Nagashima', u'id': 37265046900}, {u'author_order': 32, u'affiliation': u'NEC Electronics Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, 210-2582, Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37286514100', u'full_name': u'T. Kuwata', u'id': 37286514100}, {u'author_order': 33, u'affiliation': u'Advanced CMOS Technology Group Advanced Logic Technology Dept. System LSI Division, Toshiba Corporation', u'authorUrl': u'https://ieeexplore.ieee.org/author/37293761900', u'full_name': u'F. Matsuoka', u'id': 37293761900}] 2007 IEEE Symposium on VLSI Technology, 2007

The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized ...


Broadband CMOS class-E power amplifier for LTE applications

[{u'author_order': 1, u'affiliation': u'Mixed Signal CMOS Circuits, UMIC Research Centre, RWTH Aachen University, 52056, Germany', u'authorUrl': u'https://ieeexplore.ieee.org/author/37399321800', u'full_name': u'Danish Kalim', u'id': 37399321800}, {u'author_order': 2, u'affiliation': u'Mixed Signal CMOS Circuits, UMIC Research Centre, RWTH Aachen University, 52056, Germany', u'authorUrl': u'https://ieeexplore.ieee.org/author/37399322900', u'full_name': u'Denis Erguvan', u'id': 37399322900}, {u'author_order': 3, u'affiliation': u'Mixed Signal CMOS Circuits, UMIC Research Centre, RWTH Aachen University, 52056, Germany', u'authorUrl': u'https://ieeexplore.ieee.org/author/37275858200', u'full_name': u'Renato Negra', u'id': 37275858200}] 2009 3rd International Conference on Signals, Circuits and Systems (SCS), 2009

High level integration for system on chip (SOC) applications motivates the development of broadband power amplifiers (PAs) in low cost CMOS technology to reduce size and power consumption of any wireless system. However, integration of one of the key components in a transmitter-the PA still remains a challenge. In this paper, a single stage broadband class-E PA based on lumped ...


Recent status on Nano CMOS and future direction

[{u'author_order': 1, u'affiliation': u'Frontier Collaborative Research Center, Tokyo Institute of Technology, 4259-J2-68, Nagatsuta-cho, Midori-ku, Yokohama, 226-8502 Japan', u'authorUrl': u'https://ieeexplore.ieee.org/author/37275215700', u'full_name': u'Hiroshi Iwai', u'id': 37275215700}] 2006 International Workshop on Nano CMOS, 2006

Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length CMOS was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is still questionable if we can successfully ...


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IEEE.tv Videos

Single Die Broadband CMOS Power Amplifier and Tracker with 37% Overall Efficiency for TDD/FDD LTE Applications: RFIC Industry Forum
Analysis and Implementation of Quick-Start Pulse Generator by CMOS Flipped on Quartz Substrate: RFIC Interactive Forum
A 20dBm Configurable Linear CMOS RF Power Amplifier for Multi-Standard Transmitters: RFIC Industry Showcase
An Ultra-Wideband Low-Power ADPLL Chirp Synthesizer with Adaptive Loop Bandwidth in 65nm CMOS: RFIC Interactive Forum
CMOS mmWave Radar SoC Architecture and Applications - Sreekiran Samala - RFIC Showcase 2018
A Low Power High Performance PLL with Temperature Compensated VCO in 65nm CMOS: RFIC Interactive Forum
Compact 75GHz PA with 26.3% PAE & 24GHz Bandwidth - Stephen Callender - RFIC Showcase 2018
Multi-Standard 5Gbps to 28.2Gbps Adaptive, Single Voltage SerDes Transceiver with Analog FIR and 2-Tap Unrolled DFE in 28nm CMOS: RFIC Interactive Forum 2017
A Direct-Conversion Receiver for Multi-Carrier 3G/4G Small-Cell Base Stations in 65nm CMOS: RFIC Industry Showcase
R. Jacob Baker: CMOS & DRAM Circuit Design
A 28GHz CMOS Direct Conversion Transceiver with Packaged Antenna Arrays for 5G Cellular Systems: RFIC Industry Showcase 2017
A Ka-Band 4-Ch Bi-Directional CMOS T/R Chipset for 5G Beamforming System: RFIC Interactive Forum 2017
A High-Efficiency Linear Power Amplifier for 28GHz Mobile Communications in 40nm CMOS: RFIC Interactive Forum 2017
A 73GHz PA for 5G Phased Arrays in 14nm FinFET CMOS: RFIC Industry Showcase 2017
Q-Band CMOS Transmitter System-on-Chip - Tim Larocca - RFIC Showcase 2018
A 32GHz 20dBm-PSAT Transformer-Based Doherty Power Amplifier for MultiGb/s 5G Applications in 28nm Bulk CMOS: RFIC Interactive Forum 2017
A 60GHz Packaged Switched Beam 32nm CMOS TRX with Broad Spatial Coverage, 17.1dBm Peak EIRP, 6.1dB NF at <250mW: RFIC Industry Showcase
A Direct-Conversion Transmitter for Small-Cell Cellular Base Stations with Integrated Digital Predistortion in 65nm CMOS: RFIC Industry Showcase
Brooklyn 5G - 2015 - Ali M. Niknejad - Going the Distance with CMOS: mm-Waves and Beyond
28nm CMOS Wireless Connectivity Combo IC - Chia-Hsin Wu - RFIC Showcase 2018

IEEE-USA E-Books

  • TLU in CMOS ICs in the Electrical Fast Transient Test

    introduces the TLU under the electrical fast transient (EFT) test. The EFT test is used to demonstrate the immunity of electronic equipment to transient disturbances such as those originating from switching transients. During the EFT test, the EFT generator applies a number of fast pulses, coupled into power supply, control, signal, and ground ports of electronic equipment. Same as the system-level ESD test, TLU can be easily initiated by sweep-back current under the EFT test. Different types of noise filter networks are also investigated to find their effectiveness for improving the TLU immunity against EFT tests.

  • Appendix A: Practical ApplicationExtractions of Latchup Design Rules in a 0.18m 1.8 V/3.3V Silicided CMOS Process

    This appendix contains sections titled: * For I/O Cells * For Internal Circuits * For between I/O and Internal Circuits * For Circuits across Two Different Power Domains * Suggested Layout Guidelines ]]>

  • CMOS Basic Circuits

    This chapter contains sections titled: * Combinational Logic * Sequential Logic * Input-Output (I/O) Circuitry * Summary * References * Exercises

  • TLU Dependency on PowerPin Damping Frequency and Damping Factor in CMOS Integrated Circuits1 2007 IEEE. 4.14.3 and part of 4.4 reprinted, with permission, from ShengFu Hsu and MingDou Ker, Transientinduced latchup dependence on powerpin damping frequency and damping factor in CMOS integrated circuits (abstractsection IV and figures 2, 3, 711, and 1416), in IEEE Transactions on Electron Devices, Vol. 54, no. 8, pp. 20022010, Aug. 2007. IEEE, Piscataway, NJ.

    characterizes the TLU dependencies on two dominant parameters of TLU- triggering transient noises, power-pin damping frequency and damping factor. In real situations, they are strongly dependent on the system shielding, board-level noise filter, chip-/board- level layout, etc. Their impacts on the TLU immunity can be well explained in time domain by device simulation. Based on the comprehensive simulation results and experimental verifications, the board-level noise filters can be properly developed to efficiently eliminate the ESD-coupled noises for TLU prevention.

  • CMOS 3‐D‐Integrated MEMS Sensor

    This chapter presents one TSV‐less 3‐D complimentary metal‐oxide semiconductor (CMOS)‐on‐micro‐electro‐mechanical system (MEMS) integration technique using direct metal bonding. The CMOS‐on‐MEMS integration leads to a simultaneous formation of electrical, mechanical, and hermetic bonds, eliminates chip‐to‐chip wire‐bonding, and hence presents competitive advantages over hybrid or monolithic solutions. The MEMS sensor is a capacitive accelerometer. The basic working principle of the MEMS accelerometer is the displacement of a small proof mass etched into the silicon surface of the integrated circuit and suspended by small beams. The CMOS readout circuit for MEMS consists of a low‐noise, band‐pass gain stage, a fully differential synchronous demodulator, and an off‐chip, low‐pass filter. The chapter illustrates a figure of the heterogeneous 3‐D TSV‐less accelerometer structure. The CMOS readout circuit is stacked on the MEMS accelerometer using face‐to‐face (F2F) direct metal bonding, which provides smaller form factor, latency, and power.

  • CMOS Circuit Fabrication

    This chapter contains sections titled: * Wafer Preparation * Oxidation * Deposition, Lithography and Etching * Epitaxy, Diffusion and Ion Implantation * Contacts and Interconnects * Masks and Design Rules * Problems ]]>

  • Methods and Tools for Mixed Signal Circuit Design

  • Index

    No abstract.

  • Mixed Signals, Technology and Techniques

  • Conclusion

    This conclusion presents some closing thoughts on concepts discussed in the preceding chapters of this book. The book introduces Complementary Metal Oxide Semiconductor (CMOS)‐based scalable integration of multiple different types of sensors from different domains, or so‐called multi‐modal sensors, including impedance, terahertz, ultrasonic, optical, and electrochemical sensors, etc. They are presented from working principle, circuit design, and system implementation, as well as biomedical applications. The book summarizes the common readout circuit design with a number of demonstrated readout circuit designs for each different type of CMOS sensor in different domains. It reports the recent progress in the CMOS‐integrated multimodal biomedical sensor platform for personalized diagnosis. The CMOS‐based multimodal sensor platform has shown a promising future to integrate microfluidics, micro‐electro‐mechanical systems (MEMS), and CMOS sensors, as well as smart data analysis for personal biomedical diagnosis.



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