CMOS

View this topic in
Complementary metal–oxide–semiconductor (CMOS) is a technology for constructing integrated circuits. (Wikipedia.org)






Conferences related to CMOS

Back to Top

2019 IEEE Energy Conversion Congress and Exposition (ECCE)

IEEE-ECCE 2019 brings together practicing engineers, researchers, entrepreneurs and other professionals for interactive and multi-disciplinary discussions on the latest advances in energy conversion technologies. The Conference provides a unique platform for promoting your organization.

  • 2018 IEEE Energy Conversion Congress and Exposition (ECCE)

    The scope of ECCE 2018 includes all technical aspects of research, design, manufacture, application and marketing of devices, components, circuits and systems related to energyconversion, industrial power and power electronics.

  • 2017 IEEE Energy Conversion Congress and Exposition (ECCE)

    ECCE is the premier global conference covering topics in energy conversion from electric machines, power electronics, drives, devices and applications both existing and emergent

  • 2016 IEEE Energy Conversion Congress and Exposition (ECCE)

    The Energy Conversion Congress and Exposition (ECCE) is focused on research and industrial advancements related to our sustainable energy future. ECCE began as a collaborative effort between two societies within the IEEE: The Power Electronics Society (PELS) and the Industrial Power Conversion Systems Department (IPCSD) of the Industry Application Society (IAS) and has grown to the premier conference to discuss next generation technologies.

  • 2015 IEEE Energy Conversion Congress and Exposition

    The scope of ECCE 2015 includes all technical aspects of research, design, manufacture, application and marketing of devices, components, circuits and systems related to energy conversion, industrial power and power electronics.

  • 2014 IEEE Energy Conversion Congress and Exposition (ECCE)

    Those companies who have an interest in selling to: research engineers, application engineers, strategists, policy makers, and innovators, anyone with an interest in energy conversion systems and components.

  • 2013 IEEE Energy Conversion Congress and Exposition (ECCE)

    The scope of the congress interests include all technical aspects of the design, manufacture, application and marketing of devices, components, circuits and systems related to energy conversion, industrial power conversion and power electronics.

  • 2012 IEEE Energy Conversion Congress and Exposition (ECCE)

    The IEEE Energy Conversion Congress and Exposition (ECCE) will be held in Raleigh, the capital of North Carolina. This will provide a forum for the exchange of information among practicing professionals in the energy conversion business. This conference will bring together users and researchers and will provide technical insight as well.

  • 2011 IEEE Energy Conversion Congress and Exposition (ECCE)

    IEEE 3rd Energy Conversion Congress and Exposition follows the inagural event held in San Jose, CA in 2009 and 2nd meeting held in Atlanta, GA in 2010 as the premier conference dedicated to all aspects of energy processing in industrial, commercial, transportation and aerospace applications. ECCE2011 has a strong empahasis on renewable energy sources and power conditioning, grid interactions, power quality, storage and reliability.

  • 2010 IEEE Energy Conversion Congress and Exposition (ECCE)

    This conference covers all areas of electrical and electromechanical energy conversion. This includes power electrics, power semiconductors, electric machines and drives, components, subsystems, and applications of energy conversion systems.

  • 2009 IEEE Energy Conversion Congress and Exposition (ECCE)

    The scope of the conference include all technical aspects of the design, manufacture, application and marketing of devices, circuits, and systems related to electrical energy conversion technology


2019 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


2019 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2019 IEEE International Ultrasonics Symposium (IUS)

The conference covers all aspects of the technology associated with ultrasound generation and detection and their applications.


More Conferences

Periodicals related to CMOS

Back to Top

Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


More Periodicals

Most published Xplore authors for CMOS

Back to Top

Xplore Articles related to CMOS

Back to Top

High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)

2007 IEEE International Electron Devices Meeting, 2007

This paper describes the fabrication and performance of CMOS transistors featuring flash lamp annealing (FLA) for 45 nm node. We show, for the first time, applying FLA prior to spike RTA as S/D annealing is effective to enhance the channel stress in PFET with epitaxially grown SiGe (eSiGe) S/D. In NFET, FLA recovers the damaged layer in S/D extension caused ...


Practical implications of via-middle Cu TSV-induced stress in a 28nm CMOS technology for Wide-IO logic-memory interconnect

2012 Symposium on VLSI Technology (VLSIT), 2012

The impact of isolated and arrayed 10×60μm via-middle Cu TSVs on 8LM 28nm node CMOS poly-SiON P/NFETs was electrically measured for proximities >;4 μm at 27C and 105C. The largest observed shift in Ion(<;2.3%) is significantly less than that from other context-dependent sources such as dual stress liner boundaries (~10%). NanoBeam Diffraction measurements of Si strain within 5μm of TSVs ...


Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

2007 IEEE Symposium on VLSI Technology, 2007

The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized ...


Recent status on Nano CMOS and future direction

2006 International Workshop on Nano CMOS, 2006

Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length CMOS was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is still questionable if we can successfully ...


Broadband CMOS class-E power amplifier for LTE applications

2009 3rd International Conference on Signals, Circuits and Systems (SCS), 2009

High level integration for system on chip (SOC) applications motivates the development of broadband power amplifiers (PAs) in low cost CMOS technology to reduce size and power consumption of any wireless system. However, integration of one of the key components in a transmitter-the PA still remains a challenge. In this paper, a single stage broadband class-E PA based on lumped ...


More Xplore Articles

Educational Resources on CMOS

Back to Top

IEEE.tv Videos

Single Die Broadband CMOS Power Amplifier and Tracker with 37% Overall Efficiency for TDD/FDD LTE Applications: RFIC Industry Forum
Analysis and Implementation of Quick-Start Pulse Generator by CMOS Flipped on Quartz Substrate: RFIC Interactive Forum
A 20dBm Configurable Linear CMOS RF Power Amplifier for Multi-Standard Transmitters: RFIC Industry Showcase
A Low Power High Performance PLL with Temperature Compensated VCO in 65nm CMOS: RFIC Interactive Forum
Compact 75GHz PA with 26.3% PAE & 24GHz Bandwidth - Stephen Callender - RFIC Showcase 2018
An Ultra-Wideband Low-Power ADPLL Chirp Synthesizer with Adaptive Loop Bandwidth in 65nm CMOS: RFIC Interactive Forum
CMOS mmWave Radar SoC Architecture and Applications - Sreekiran Samala - RFIC Showcase 2018
Multi-Standard 5Gbps to 28.2Gbps Adaptive, Single Voltage SerDes Transceiver with Analog FIR and 2-Tap Unrolled DFE in 28nm CMOS: RFIC Interactive Forum 2017
A Direct-Conversion Receiver for Multi-Carrier 3G/4G Small-Cell Base Stations in 65nm CMOS: RFIC Industry Showcase
R. Jacob Baker: CMOS & DRAM Circuit Design
A Ka-Band 4-Ch Bi-Directional CMOS T/R Chipset for 5G Beamforming System: RFIC Interactive Forum 2017
A High-Efficiency Linear Power Amplifier for 28GHz Mobile Communications in 40nm CMOS: RFIC Interactive Forum 2017
A 73GHz PA for 5G Phased Arrays in 14nm FinFET CMOS: RFIC Industry Showcase 2017
Q-Band CMOS Transmitter System-on-Chip - Tim Larocca - RFIC Showcase 2018
A 28GHz CMOS Direct Conversion Transceiver with Packaged Antenna Arrays for 5G Cellular Systems: RFIC Industry Showcase 2017
A 32GHz 20dBm-PSAT Transformer-Based Doherty Power Amplifier for MultiGb/s 5G Applications in 28nm Bulk CMOS: RFIC Interactive Forum 2017
A 60GHz Packaged Switched Beam 32nm CMOS TRX with Broad Spatial Coverage, 17.1dBm Peak EIRP, 6.1dB NF at <250mW: RFIC Industry Showcase
A Direct-Conversion Transmitter for Small-Cell Cellular Base Stations with Integrated Digital Predistortion in 65nm CMOS: RFIC Industry Showcase
Brooklyn 5G - 2015 - Ali M. Niknejad - Going the Distance with CMOS: mm-Waves and Beyond
28nm CMOS Wireless Connectivity Combo IC - Chia-Hsin Wu - RFIC Showcase 2018

IEEE-USA E-Books

  • High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)

    This paper describes the fabrication and performance of CMOS transistors featuring flash lamp annealing (FLA) for 45 nm node. We show, for the first time, applying FLA prior to spike RTA as S/D annealing is effective to enhance the channel stress in PFET with epitaxially grown SiGe (eSiGe) S/D. In NFET, FLA recovers the damaged layer in S/D extension caused by implantation and suppresses the transient enhanced diffusion (TED). These improvements result in 11% and 8% higher saturation drive current, and IDSAT=750muA/mum and 1160muA/mum for IOFF=100 nAmum at Vdd=lV in PFET and NFET, respectively. We also report the pattern density dependence of performance gain from FLA technique.

  • Practical implications of via-middle Cu TSV-induced stress in a 28nm CMOS technology for Wide-IO logic-memory interconnect

    The impact of isolated and arrayed 10×60μm via-middle Cu TSVs on 8LM 28nm node CMOS poly-SiON P/NFETs was electrically measured for proximities >;4 μm at 27C and 105C. The largest observed shift in Ion(<;2.3%) is significantly less than that from other context-dependent sources such as dual stress liner boundaries (~10%). NanoBeam Diffraction measurements of Si strain within 5μm of TSVs were acquired for samples prepared from fully processed wafers, showing that for proximity >;1.5μm the impact of TSVs is negligible. Interaction with overlying interconnect is mitigated through optimization of post-TSV plating anneal to achieve <; 200 ÅCu pumping and by introducing a TSV unit cell designed to minimize the impact on local environment.

  • Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

    The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized in aggressively scaled CMOS with dense gate pitch rule (190 nm) in 45 nm technology node.

  • Recent status on Nano CMOS and future direction

    Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length CMOS was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is still questionable if we can successfully introduce sub-10 nm CMOS LSIs into market, because the problems expected at this moment - such as I<sub>on</sub>/I<sub>off</sub> ratio, current drive, variation in the electrical characteristics, concerns for the yield, reliability and manufacturing cost. Considering the above situation, we formed a leading research group for future ultra-low power nano- CMOS technology in 2003 - 2006, by the Special Coordination Funds for Promoting Science and Technology sponsored by Ministry of Education, Culture, Sports, Science and Technology, Japan, in order to conduct nano-CMOS studies in advance to provide possible solutions to the future expected problems. The conclusion obtained by the group study was that, in the Nano-CMOS era, aggressive introduction of new materials, processes, structures, and operation concepts is required to solve the problems. Also, new physical analysis technique and physical model in order to predict and explain the atomic scale phenomena and properties at the new material interfaces are important. Unfortunately, there are no candidates among the so-called 'beyond CMOS' new devices, which are believed to really replace CMOS transistors usable for the products of highly integrated circuits within 20 years. Thus, our opinion is that we need to still continue CMOS based transistors - CMOS with FinFET, Nanowire FET, and even CNTFET - with 'More Moore' approach with combining that of 'More than Moore'.

  • Broadband CMOS class-E power amplifier for LTE applications

    High level integration for system on chip (SOC) applications motivates the development of broadband power amplifiers (PAs) in low cost CMOS technology to reduce size and power consumption of any wireless system. However, integration of one of the key components in a transmitter-the PA still remains a challenge. In this paper, a single stage broadband class-E PA based on lumped element load transformation network (LTN) in 90 nm CMOS technology for LTE band i.e. 2.67 GHz is presented. The simulations with a 2.5 V supply voltage show that the designed PA can deliver an output power (P<sub>out</sub>) of 22.9 dBm with an associated power gain (G) of 8.9 dB and power added efficiency (PAE) of 60.4 %. A PAE of more than 55 %, output power of 21.5 dBm and a gain of more than 7.5 dB was achieved over a wide bandwidth i.e. from 2.3 GHz to 3.3 GHz. The frequency range also covers wireless local area network (WLAN) and bluetooth applications.

  • Low power NDIR CO<inf>2</inf>sensor based on CMOS IR emitter for boiler applications

    In this paper we demonstrate the use of a CMOS infra-red emitter in a low power Non Dispersive Infra Red (NDIR) based carbon dioxide sensor for application in domestic boilers. Compared to conventional micro-bulbs as IR wideband sources, CMOS IR emitters offer several advantages: They are faster, smaller, have lower power consumption and can have integrated circuitry. The emitter is a 1.16 mm × 1.06 mm chip with an integrated FET drive and consists of a tungsten heater fabricated in a CMOS process followed by Deep Reactive Ion Etching (DRIE) to form a thin membrane to reduce power consumption. The NDIR sensor consists of the emitter and a commercial detector placed 5 mm apart in a simple tube. Operating the emitter at 10 Hz with a power consumption of only 40 mW, the sensor was measured in the range of 6-14% by volume of CO2, showing a resolution of 0.5%, a response time of 20 s, and low cross-sensitivity to humidity.

  • Study on CMOS class-E power amplifiers for LTE applications

    Integrating power amplifiers (PAs) is one of the challenges for system-on-chip (SOC) applications due to the low breakdown voltage of nanoscale CMOS devices. This paper presents the study and design of three class-E PAs based on lumped element load transformation networks (LTNs) in 90nm CMOS process for LTE band, i.e. 2.55 GHz. The simulation results show that the designed PAs can deliver an output power (P<sub>out</sub>) of more than 20.1dBm and power added efficiency (PAE) greater than 43.6% when operated from 2.5V supply. The results are analysed and evaluated to compare the performance of the implemented class-E PAs in terms of PAE, power gain (G) and harmonic rejection for LTE applications.

  • Quo vadis nano-CMOS ?

    When I was a student, 25 years ago, one of the hypotheses was that intelligence would appear spontaneously once complexity and speed of a logic system exceed a given level. In the span of last 25 years the CMOS switching frequency has increased X50, the number of transistors per chip X1000, whereas the transistor feature size has decreased X32. In spite of that extraordinary progress, our computers seem all but intelligent. Does it mean that we are still below this magic complexity level? Maybe, but taking into account that CMOS is already today a genuine Nano-technology, there is little room left for improvement. Therefore, will intelligence appear within the remaining 3 or so generations before Nano-CMOS hits the atomic limit? Or maybe we should admit that transistor performance is no longer a key, and targets for CMOS technologies should be refined? If so, what is then THE nano-device we should seek? What is THE nano-technology we should target? In this paper we will deliberate on these and relevant questions (hardly answering ANY).

  • A Low-Power, Low-Cost Infra-Red Emitter in CMOS Technology

    In this paper, we present the design and characterization of a low-power low- cost infra-red emitter based on a tungsten micro-hotplate fabricated in a commercial 1-μm silicon on insulator-CMOS technology. The device has a 250-μm diameter resistive heater inside a 600-μm diameter thin dielectric membrane. We first present electro-thermal and optical device characterization, long term stability measurements, and then demonstrate its application as a gas sensor for a domestic boiler. The emitter has a dc power consumption of only 70 mW, a total emission of 0.8 mW across the 2.5-15-μm wavelength range, a 50% frequency modulation depth of 70 Hz, and excellent reproducibility from device-to-device. We also compare two larger emitters (heater size of 600 and 1800 μm) made in the same technology that have a much higher infra-red emission, but at the detriment of higher power consumption. Finally, we demonstrate that carbon nanotubes can be used to significantly enhance the thermo-optical transduction efficiency of the emitter.

  • Analysis and design of an unconditionally stable common-drain class-B RF power amplifier in 90 nm CMOS technology

    Modern communication networks demand power amplifiers (PAs) which are efficient and have low distortion. The common drain amplifier has the potential to become a linear amplifier with good efficiency, when biased at or above class-B. The main challenge is to provide unconditional stability while still maintaining adequate transducer gain so that the power added efficiency (PAE) will not be compromised by low gain and, thus, resulting in better overall performance. In this contribution, analysis and design of an unconditionally stable common drain class-B PA for the LTE band at 2.55 GHz in 90 nm CMOS is presented. The simulation results show that the designed PA can deliver an output power of more than 27.2 dBm with gain of 6.1 dB and PAE greater than 43.0 % when operated from 2.5 V supply. The circuit has a third order intermodulation distrotion suppression of 32.0 dBc at 3 dB input back- off.



Standards related to CMOS

Back to Top

No standards are currently tagged "CMOS"


Jobs related to CMOS

Back to Top