Verilog

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In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. (Wikipedia.org)






Conferences related to Verilog

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2012 13th International Symposium on Quality Electronic Design (ISQED)

The International Symposium on Quality Electronic Design (ISQED) the premier Electronic Design conference bridges the gap between Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve design quality.

  • 2011 International Symposium on Quality Electronic Design (ISQED)

    ISQED is a premier Design & Design Automation conference bridges the gap between electronic design tools and processes, integrated circuit technologies, processes & manufacturing, to achieve design quality. ISQED is the leading conference for design for manufacturability (DFM) and quality (DFQ) issues. It provides a forum to exchange ideas and promote research, development, and application of design techniques & methods, design processes, and EDA design methodologies and tools that address issues which impa

  • 2010 11th International Symposium on Quality of Electronic Design (ISQED)

    ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues, front to back.

  • 2009 10th International Symposium on Quality of Electronic Design (ISQED)

    The International Symposium on Quality Electronic Design (ISQED), is a premier Design & Design Automation conference, aimed at bridging the gap between and integration of, electronic design tools and processes, integrated circuit technologies, processes & manufacturing, to achieve design quality. ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues, front to back. The conference provides a forum to present and exchange ideas and to promote the research, de

  • 2008 9th International Symposium on Quality of Electronic Design (ISQED)

    The International Symposium on Quality Electronic Design (ISQED), is a premier Design & Design Automation conference, aimed at bridging the gap between and integration of, electronic design tools and processes, integrated circuit technologies, processes & manufacturing, to achieve design quality. ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues, front to back. The conference provides a forum to present and exchange ideas and to promote the research.


2012 6th International Conference on Software Security and Reliability (SERE)

Focuses on software security, safety, reliability, and quality assurance for researchers and practitioners to exchange ideas and best-of-breed practices for developing trustworthy software in a more effective and efficient way.


2011 IEEE International Conference on Microelectronic Systems Education (MSE)

The International Conference on Microelectronic Systems Education (MSE) is dedicated to furthering undergraduate and graduate education in designing and building innovative microelectronic systems. The conference is held in the U.S. on odd years, and in Europe on even years, when it is called the European Workshop on Microelectronics Education. This conference provides an excellent opportunity for educators and industry to work together to ensure continued excellence in the field of microelectronic syste



Periodicals related to Verilog

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Xplore Articles related to Verilog

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A new level sensitive D Latch using Ballistic nanodevices

Poorna Marthi; Nazir Hossain; Jean-Francois Millithaler; Martin Margala 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016

In this paper, a D-Latch design using Ballistic Deflection Transistors (BDT) is presented. BDT technology was developed and experimentally proven to operate at THz frequencies. A simple, compact fit based analytical BDT model, developed previously to aid circuit design was utilized in this paper. The empirical device model is integrated into a behavioral Verilog A module to facilitate the investigation ...


Implementation of a testing environment for digital IP cores

S. R. Das; Chuan Jin; Liwu Jin; M. H. Assaf; E. M. Petriu; Wen-Ben Jone; M. Sahinoglu Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.04CH37510), 2004

This paper proposes a Verilog HDL-based fault simulation and testing environment for embedded IP core-based digital systems, specifically targeted towards synchronous memory-based systems, for detecting single stuck-line faults. The simulator emulates a typical BIST (built-in self-testing) environment with test pattern generator that sends its outputs to a MUT (module under test) and the output streams from the MUT are fed ...


An improved compact model of cross-shaped horizontal CMOS-integrated Hall-effect sensor

Morgan Madec; Jean-Baptiste Kammerer; Luc Hebrard Proceedings of the 8th IEEE International NEWCAS Conference 2010, 2010

A new compact model of a cross-shaped horizontal integrated Hall-effect sensor is presented in this paper. Compared to existing models, the model reliability is improved, especially for designs in which the bias and the measurement circuits are not independent. The Hall device model uses six subcomponents, each modeling the non-linear resistance due to the sensor space charge region modulation and ...


High speed DNA sequencing accelerator using FPGA

Syed Abdul Mutalib Al Junid; Zulkifli Abd Majid; Abdul Karimi Halim 2008 International Conference on Electronic Design, 2008

This paper presents the development of High Speed DNA sequencing accelerator based on Smith-Waterman algorithm using FPGA. The scope of the paper focuses on speed optimization with parallelism. Smith-Waterman algorithm is sensitive algorithm used for procedure of DNA sequence alignments in computational molecular biology. As the number of sequence database increase exponentially, it affects the performance of Smith-Waterman algorithm in ...


A Semiphysical Large-Signal Compact Carbon Nanotube FET Model for Analog RF Applications

Michael Schröter; Max Haferlach; Aníbal Pacheco-Sanchez; Sven Mothes; Paulius Sakalas; Martin Claus IEEE Transactions on Electron Devices, 2015

A compact large-signal model, called Compact Carbon Nanotube Model (CCAM), is presented that accurately describes the shape of DC and small-signal characteristics of fabricated carbon nano-tube FETs (CNTFETs). The new model consists of computationally efficient and smooth current and charge formulations. The model allows, for a given gate length, geometry scaling from single-finger single-tube to multifinger multitube transistors. Ambipolar transport, ...


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Educational Resources on Verilog

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eLearning

A new level sensitive D Latch using Ballistic nanodevices

Poorna Marthi; Nazir Hossain; Jean-Francois Millithaler; Martin Margala 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016

In this paper, a D-Latch design using Ballistic Deflection Transistors (BDT) is presented. BDT technology was developed and experimentally proven to operate at THz frequencies. A simple, compact fit based analytical BDT model, developed previously to aid circuit design was utilized in this paper. The empirical device model is integrated into a behavioral Verilog A module to facilitate the investigation ...


Implementation of a testing environment for digital IP cores

S. R. Das; Chuan Jin; Liwu Jin; M. H. Assaf; E. M. Petriu; Wen-Ben Jone; M. Sahinoglu Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.04CH37510), 2004

This paper proposes a Verilog HDL-based fault simulation and testing environment for embedded IP core-based digital systems, specifically targeted towards synchronous memory-based systems, for detecting single stuck-line faults. The simulator emulates a typical BIST (built-in self-testing) environment with test pattern generator that sends its outputs to a MUT (module under test) and the output streams from the MUT are fed ...


An improved compact model of cross-shaped horizontal CMOS-integrated Hall-effect sensor

Morgan Madec; Jean-Baptiste Kammerer; Luc Hebrard Proceedings of the 8th IEEE International NEWCAS Conference 2010, 2010

A new compact model of a cross-shaped horizontal integrated Hall-effect sensor is presented in this paper. Compared to existing models, the model reliability is improved, especially for designs in which the bias and the measurement circuits are not independent. The Hall device model uses six subcomponents, each modeling the non-linear resistance due to the sensor space charge region modulation and ...


High speed DNA sequencing accelerator using FPGA

Syed Abdul Mutalib Al Junid; Zulkifli Abd Majid; Abdul Karimi Halim 2008 International Conference on Electronic Design, 2008

This paper presents the development of High Speed DNA sequencing accelerator based on Smith-Waterman algorithm using FPGA. The scope of the paper focuses on speed optimization with parallelism. Smith-Waterman algorithm is sensitive algorithm used for procedure of DNA sequence alignments in computational molecular biology. As the number of sequence database increase exponentially, it affects the performance of Smith-Waterman algorithm in ...


A Semiphysical Large-Signal Compact Carbon Nanotube FET Model for Analog RF Applications

Michael Schröter; Max Haferlach; Aníbal Pacheco-Sanchez; Sven Mothes; Paulius Sakalas; Martin Claus IEEE Transactions on Electron Devices, 2015

A compact large-signal model, called Compact Carbon Nanotube Model (CCAM), is presented that accurately describes the shape of DC and small-signal characteristics of fabricated carbon nano-tube FETs (CNTFETs). The new model consists of computationally efficient and smooth current and charge formulations. The model allows, for a given gate length, geometry scaling from single-finger single-tube to multifinger multitube transistors. Ambipolar transport, ...


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IEEE.tv Videos

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IEEE-USA E-Books

  • Frontmatter

    The prelims comprise: Half-Title IEEE Press Editorial Board Title Copyright Dedication Contents Preface Acknowledgments

  • Switch Level Modeling

    This chapter contains sections titled: Introduction Basic Transistor Switches CMOS Switch Bidirectional Gates Time Delays with Switch Primitives Instantiations with Strengths And Delays Strength Contention with Trireg Nets Exercises

  • Introduction to VLSI Design

    This chapter contains sections titled: Introduction Conventional Approach to Digital Design VLSI Design ASIC Design Flow Role of HDL

  • System Tasks, Functions, and Compiler Directives

    This chapter contains sections titled: Introduction Parameters Path Delays Module Parameters System Tasks and Functions File-Based Tasks and Functions Compiler Directives Hierarchical Access General Observations Exercises

  • Introduction to Verilog

    This chapter contains sections titled: Verilog as an HDL Levels of Design Description Concurrency Simulation and Synthesis Functional Verification System Tasks Programming Language Interface (PLI) Module Simulation and Synthesis Tools Test Benches

  • Queues, PLAs, and FSMS

    This chapter contains sections titled: Introduction Queues Programmable Logic Devices (PLDs) Design of Finite State Machines Exercises

  • Index

    No abstract.

  • Appendix: Verilog HDL Design

    This appendix contains sections titled: Introduction to Verilog Design Design Level Design Flow Verilog Syntax Example of Four-bit Adder with Zero Detection Synthesis Scripts

  • Digital Autotuning

    This introduction presents an overview of the concepts discussed in this book. The book is focused on the fundamental aspects of analysis, modeling, and design of digital control loops around high-frequency switched-mode power converters in a systematic and rigorous manner. This chapter introduces the topics covered in the book and to motivate the reader to pursue the theoretical and practical concepts covered in the remaining chapters of this book. Given the focus of the book on high-frequency switched-mode power converter applications, the emphasis is on hardwired implementations of the control law, together with VHDL and Verilog coding examples. The principles that apply to software-based, microprogrammed realizations are highlighted. Practical examples illustrate applications of the techniques developed. The chapter highlights some of the gains enabled by digital control in the areas of improved dynamic responses, integration of frequency-response measurements, autotuning of digital control loops, and on-line efficiency optimization.

  • Language Constructs and Conventions in Verilog

    This chapter contains sections titled: Introduction Keywords Identifiers White Space Characters Comments Numbers Strings Logic Values Strengths Data Types Scalars and Vectors Parameters Memory Operators System Tasks Exercises



Standards related to Verilog

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IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language

SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including ...


IEEE Standard for Verilog Hardware Description Language

Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005. The intent of this standard is to serve as a complete specification ...


IEEE Standard for Verilog Register Transfer Level Synthesis

To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.


IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

The standard describes a standard syntax and semantics for VHDL RTL synthesis. It defines the subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis and defines the semantics of that subset for the synthesis domain. The intent of this revision is to include a maximum subset of VHDL that can be used to describe synthesizable RTL logic. This ...


IEEE Standard Interface for Hardware Description Models of Electronic Components

Development of a standard simulation and related tool interface for component models written in VHDL, Verilog, C and other description languages.


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Jobs related to Verilog

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