Verilog

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In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. (Wikipedia.org)






Conferences related to Verilog

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2012 13th International Symposium on Quality Electronic Design (ISQED)

The International Symposium on Quality Electronic Design (ISQED) the premier Electronic Design conference bridges the gap between Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve design quality.

  • 2011 International Symposium on Quality Electronic Design (ISQED)

    ISQED is a premier Design & Design Automation conference bridges the gap between electronic design tools and processes, integrated circuit technologies, processes & manufacturing, to achieve design quality. ISQED is the leading conference for design for manufacturability (DFM) and quality (DFQ) issues. It provides a forum to exchange ideas and promote research, development, and application of design techniques & methods, design processes, and EDA design methodologies and tools that address issues which impa

  • 2010 11th International Symposium on Quality of Electronic Design (ISQED)

    ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues, front to back.

  • 2009 10th International Symposium on Quality of Electronic Design (ISQED)

    The International Symposium on Quality Electronic Design (ISQED), is a premier Design & Design Automation conference, aimed at bridging the gap between and integration of, electronic design tools and processes, integrated circuit technologies, processes & manufacturing, to achieve design quality. ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues, front to back. The conference provides a forum to present and exchange ideas and to promote the research, de

  • 2008 9th International Symposium on Quality of Electronic Design (ISQED)

    The International Symposium on Quality Electronic Design (ISQED), is a premier Design & Design Automation conference, aimed at bridging the gap between and integration of, electronic design tools and processes, integrated circuit technologies, processes & manufacturing, to achieve design quality. ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues, front to back. The conference provides a forum to present and exchange ideas and to promote the research.


2012 6th International Conference on Software Security and Reliability (SERE)

Focuses on software security, safety, reliability, and quality assurance for researchers and practitioners to exchange ideas and best-of-breed practices for developing trustworthy software in a more effective and efficient way.


2011 IEEE International Conference on Microelectronic Systems Education (MSE)

The International Conference on Microelectronic Systems Education (MSE) is dedicated to furthering undergraduate and graduate education in designing and building innovative microelectronic systems. The conference is held in the U.S. on odd years, and in Europe on even years, when it is called the European Workshop on Microelectronics Education. This conference provides an excellent opportunity for educators and industry to work together to ensure continued excellence in the field of microelectronic syste


2007 IEEE International Behavioral Modeling and Simulation Workshop (BMAS 2007)

Designers and CAD developers in the behavioral modeling and simulation of circuits and systems.



Periodicals related to Verilog

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Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.




Xplore Articles related to Verilog

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VLSI Based Robust Router Architecture

Channamallikarjuna Mattihalli; Suprith Ron; Naveen Kolla 2012 Third International Conference on Intelligent Systems Modelling and Simulation, 2012

In his paper we attempt to give a networking solution by applying VLSI architecture techniques to router design for networking systems to provide intelligent control over the network. Networking routers today have limited input/output configurations, which we attempt to overcome by adopting bridging loops to reduce the latency and security concerns. Other techniques we explore include the use of multiple ...


Integrating a full custom microprocessor in a user defined ASIC array as a fully diffused core

L. Ashby; D. Kuner [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit, 1992

A MC68000 microprocessor has been embedded in a gate array device as a fully diffused core, allowing ASIC designers to combine up to 60 K gates of user- defined logic, verified within the Verilog simulation environment. The MC68000 can be implemented on other array sizes utilizing the same flow. For each new array the layout flow is repeated to generate ...


Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells

Bruce F. Cockburn; Keith Boyle 2006 Canadian Conference on Electrical and Computer Engineering, 2006

A delay locked loop (DLL) is a feedback control system that equalizes the phase of two delayed copies of the same clock signal. The DLL is useful for compensating for the clock distribution delays that arise in many system configurations. Our motivation for designing an all-digital DLL was to ensure that the clock signal (and hence input vectors) received from ...


Model Checking Verilog Descriptions of Cell Libraries

Matthias Raffelsieper; Jan-Willem Roorda; MohammadReza Mousavi 2009 Ninth International Conference on Application of Concurrency to System Design, 2009

We present a formal semantics for a subset of Verilog, commonly used to describe cell libraries, in terms of transition systems. Such transition systems can serve as input to symbolic model checking, for example equivalence checking with a transistor netlist description. We implement our formal semantics as an encoding from the subset of Verilog to the input language of the ...


So many states, so little time: verifying memory coherence in the Cray X1

D. Abts; S. Scott; D. J. Lilja Proceedings International Parallel and Distributed Processing Symposium, 2003

This paper investigates a complexity-effective technique for verifying a highly distributed directory-based cache coherence protocol. We develop a novel approach called "witness strings" that combines both formal and informal verification methods to expose design errors within the cache coherence protocol and its Verilog implementation. In this approach a formal execution trace is extracted during model checking of the architectural model ...


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Educational Resources on Verilog

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eLearning

VLSI Based Robust Router Architecture

Channamallikarjuna Mattihalli; Suprith Ron; Naveen Kolla 2012 Third International Conference on Intelligent Systems Modelling and Simulation, 2012

In his paper we attempt to give a networking solution by applying VLSI architecture techniques to router design for networking systems to provide intelligent control over the network. Networking routers today have limited input/output configurations, which we attempt to overcome by adopting bridging loops to reduce the latency and security concerns. Other techniques we explore include the use of multiple ...


Integrating a full custom microprocessor in a user defined ASIC array as a fully diffused core

L. Ashby; D. Kuner [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit, 1992

A MC68000 microprocessor has been embedded in a gate array device as a fully diffused core, allowing ASIC designers to combine up to 60 K gates of user- defined logic, verified within the Verilog simulation environment. The MC68000 can be implemented on other array sizes utilizing the same flow. For each new array the layout flow is repeated to generate ...


Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells

Bruce F. Cockburn; Keith Boyle 2006 Canadian Conference on Electrical and Computer Engineering, 2006

A delay locked loop (DLL) is a feedback control system that equalizes the phase of two delayed copies of the same clock signal. The DLL is useful for compensating for the clock distribution delays that arise in many system configurations. Our motivation for designing an all-digital DLL was to ensure that the clock signal (and hence input vectors) received from ...


Model Checking Verilog Descriptions of Cell Libraries

Matthias Raffelsieper; Jan-Willem Roorda; MohammadReza Mousavi 2009 Ninth International Conference on Application of Concurrency to System Design, 2009

We present a formal semantics for a subset of Verilog, commonly used to describe cell libraries, in terms of transition systems. Such transition systems can serve as input to symbolic model checking, for example equivalence checking with a transistor netlist description. We implement our formal semantics as an encoding from the subset of Verilog to the input language of the ...


So many states, so little time: verifying memory coherence in the Cray X1

D. Abts; S. Scott; D. J. Lilja Proceedings International Parallel and Distributed Processing Symposium, 2003

This paper investigates a complexity-effective technique for verifying a highly distributed directory-based cache coherence protocol. We develop a novel approach called "witness strings" that combines both formal and informal verification methods to expose design errors within the cache coherence protocol and its Verilog implementation. In this approach a formal execution trace is extracted during model checking of the architectural model ...


More eLearning Resources

IEEE.tv Videos

No IEEE.tv Videos are currently tagged "Verilog"

IEEE-USA E-Books

  • No title

    Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A wor ing knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. Table of Contents: Calculating Maximum Clock Frequency / Improving Design Performance / Finite State Machine with Datapath (FSMD) Design / Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs

  • References

    No abstract.

  • Digital Autotuning

    This introduction presents an overview of the concepts discussed in this book. The book is focused on the fundamental aspects of analysis, modeling, and design of digital control loops around high-frequency switched-mode power converters in a systematic and rigorous manner. This chapter introduces the topics covered in the book and to motivate the reader to pursue the theoretical and practical concepts covered in the remaining chapters of this book. Given the focus of the book on high-frequency switched-mode power converter applications, the emphasis is on hardwired implementations of the control law, together with VHDL and Verilog coding examples. The principles that apply to software-based, microprogrammed realizations are highlighted. Practical examples illustrate applications of the techniques developed. The chapter highlights some of the gains enabled by digital control in the areas of improved dynamic responses, integration of frequency-response measurements, autotuning of digital control loops, and on-line efficiency optimization.

  • Modeling at Data Flow Level

    This chapter contains sections titled: Introduction Continuous Assignment Structures Delays and Continuous Assignments Assignment to Vectors Operators Additional Examples Exercises

  • Behavioral Modeling II

    This chapter contains sections titled: Introduction if and if-else Constructs assign-deassign Construct repeat Construct for Loop The disable Construct while Loop forever Loop Parallel Blocks force-release Construct Event Exercises

  • Switch Level Modeling

    This chapter contains sections titled: Introduction Basic Transistor Switches CMOS Switch Bidirectional Gates Time Delays with Switch Primitives Instantiations with Strengths And Delays Strength Contention with Trireg Nets Exercises

  • Frontmatter

    The prelims comprise: Half-Title IEEE Press Editorial Board Title Copyright Dedication Contents Preface Acknowledgments

  • Appendix: Verilog HDL Design

    This appendix contains sections titled: Introduction to Verilog Design Design Level Design Flow Verilog Syntax Example of Four-bit Adder with Zero Detection Synthesis Scripts

  • Queues, PLAs, and FSMS

    This chapter contains sections titled: Introduction Queues Programmable Logic Devices (PLDs) Design of Finite State Machines Exercises

  • Introduction to Verilog

    This chapter contains sections titled: Verilog as an HDL Levels of Design Description Concurrency Simulation and Synthesis Functional Verification System Tasks Programming Language Interface (PLI) Module Simulation and Synthesis Tools Test Benches



Standards related to Verilog

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IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language

SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including ...


IEEE Standard for Verilog Hardware Description Language

Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005. The intent of this standard is to serve as a complete specification ...


IEEE Standard for Verilog Register Transfer Level Synthesis

To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.


IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

The standard describes a standard syntax and semantics for VHDL RTL synthesis. It defines the subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis and defines the semantics of that subset for the synthesis domain. The intent of this revision is to include a maximum subset of VHDL that can be used to describe synthesizable RTL logic. This ...


IEEE Standard Interface for Hardware Description Models of Electronic Components

Development of a standard simulation and related tool interface for component models written in VHDL, Verilog, C and other description languages.


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Jobs related to Verilog

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