Conferences related to Space Exploration

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2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems & Eurosensors XXXIII (TRANSDUCERS & EUROSENSORS XXXIII)

The world's premiere conference in MEMS sensors, actuators and integrated micro and nano systems welcomes you to attend this four-day event showcasing major technological, scientific and commercial breakthroughs in mechanical, optical, chemical and biological devices and systems using micro and nanotechnology.The major areas of activity in the development of Transducers solicited and expected at this conference include but are not limited to: Bio, Medical, Chemical, and Micro Total Analysis Systems Fabrication and Packaging Mechanical and Physical Sensors Materials and Characterization Design, Simulation and Theory Actuators Optical MEMS RF MEMS Nanotechnology Energy and Power


2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2019 IEEE 46th Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2019 IEEE 58th Conference on Decision and Control (CDC)

The CDC is recognized as the premier scientific and engineering conference dedicated to the advancement of the theory and practice of systems and control. The CDC annually brings together an international community of researchers and practitioners in the field of automatic control to discuss new research results, perspectives on future developments, and innovative applications relevant to decision making, systems and control, and related areas.The 58th CDC will feature contributed and invited papers, as well as workshops and may include tutorial sessions.The IEEE CDC is hosted by the IEEE Control Systems Society (CSS) in cooperation with the Society for Industrial and Applied Mathematics (SIAM), the Institute for Operations Research and the Management Sciences (INFORMS), the Japanese Society for Instrument and Control Engineers (SICE), and the European Union Control Association (EUCA).


2019 IEEE International Conference on Industrial Technology (ICIT)

The scope of the conference will cover, but will not be limited to, the following topics: Robotics; Mechatronics; Industrial Automation; Autonomous Systems; Sensing and artificial perception, Actuators and Micro-nanotechnology; Signal/Image Processing and Computational Intelligence; Control Systems; Electronic System on Chip and Embedded Control; Electric Transportation; Power Electronics; Electric Machines and Drives; Renewable Energy and Smart Grid; Data and Software Engineering, Communication; Networking and Industrial Informatics.


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Periodicals related to Space Exploration

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Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Antennas and Wireless Propagation Letters, IEEE

IEEE Antennas and Wireless Propagation Letters (AWP Letters) will be devoted to the rapid electronic publication of short manuscripts in the technical areas of Antennas and Wireless Propagation.


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer Graphics and Applications, IEEE

IEEE Computer Graphics and Applications (CG&A) bridges the theory and practice of computer graphics. From specific algorithms to full system implementations, CG&A offers a strong combination of peer-reviewed feature articles and refereed departments, including news and product announcements. Special Applications sidebars relate research stories to commercial development. Cover stories focus on creative applications of the technology by an artist or ...


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Most published Xplore authors for Space Exploration

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Xplore Articles related to Space Exploration

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Optimization of Δvega trajectory based on analytical gradients

2006 International Conference on Machine Learning and Cybernetics, 2006

In deep space exploration missions, total ΔV is a very important performance index. Δ VEGA and optimization are two important technique to reduce the total Δ V in deep space missions. The earth swingby increase the sensitivity of the trajectory greatly, so the optimization of Δ VEGA trajectory is one of the most sophisticated problem currently investigated in the region. ...


Effects of EPP on place orientation and space exploration dysfunctions in mice

Proceedings 2011 International Conference on Human Health and Biomedical Engineering, 2011

Pentobarbital was used to induce the place orientation and space exploration dysfunctions. Morris water maze was used to observe mice's abilities of place orientation and space exploration. Bradford method was used for the determination of the total protein and spectrometry method was used for the detection of acetylcholinesterase (AChE) activity. Extract of Polygala tenuifolia and Poria cocos (EPP) could shorten ...


Design Space Exploration of a Reconfigurable HMAC-Hash Unit

2006 ITI 4th International Conference on Information & Communications Technology, 2006

In this paper, a design space exploration of a reconfigurable HMAC-hash unit is discussed. This unit implements one of six standard hash algorithms, namely, MD5, SHA-1, RIPEMD-160, HMAC-MD5, HMAC-SHA-1, and HMAC-RIPEMD-160. The design space exploration of this unit is done using the Handel-C language. We propose key reuse mechanism for successive messages in order to improve the HMAC throughput. In ...


Novel Heuristic Mapping Algorithms for Design Space Exploration of Multiprocessor Embedded Architectures

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2016

Electronic System level design has an important role in the multi-processor embedded system on chip design. Two important steps in this process are evaluation of a single design configuration and design space exploration. In the first part of design process, high-level simple analytical models for application mapping and evaluation are used and modified aiming at accelerating the evaluation of a ...


Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010

Increasing diversity in packet-processing applications and rapid increases in channel bandwidth lead to greater complexity in communication protocols. These factors result in larger computational loads for packet-processing engines that introduce high performance microprocessor designs as an important solution. This paper presents an exhaustive simulation for exploring the performance of instruction-level parallel super scalar processors executing packet-processing applications. Based on the ...


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Educational Resources on Space Exploration

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IEEE-USA E-Books

  • Optimization of Δvega trajectory based on analytical gradients

    In deep space exploration missions, total ΔV is a very important performance index. Δ VEGA and optimization are two important technique to reduce the total Δ V in deep space missions. The earth swingby increase the sensitivity of the trajectory greatly, so the optimization of Δ VEGA trajectory is one of the most sophisticated problem currently investigated in the region. In this paper, the whole Δ VEGA trajectory is divided into several trajectory segments. Each trajectory segment connecting consecutive maneuver points is found by solving an N-body analog to Lambert's problem. We can also obtain state transition matrix of each trajectory segments. The analytical gradients of total Δ V with respect to adjustable variables such as launch time, arrival time, swingby time and the periapsis position relative to the gravitating body are derived based on the transition matrix and calculus of variation. The performance index could be reduced by utilizing quasi-Newton algorithm. At the end of this paper, the Δ VEGA trajectory of Chinese deep space exploration mission to the near earth asteroid Ivar is optimized by this method.

  • Effects of EPP on place orientation and space exploration dysfunctions in mice

    Pentobarbital was used to induce the place orientation and space exploration dysfunctions. Morris water maze was used to observe mice's abilities of place orientation and space exploration. Bradford method was used for the determination of the total protein and spectrometry method was used for the detection of acetylcholinesterase (AChE) activity. Extract of Polygala tenuifolia and Poria cocos (EPP) could shorten the escape latency in place orientation test and increase numbers of mice's crossing the location where the platform had been in the space exploration test. EPP could decrease AChE activities in the brain and the serum of mice with learning and memory disorders induced by pentobarbital. EPP would improve the learning and memory abilities of mice induced by chemical drugs. The results demonstrate that EPP would improve place orientation and space exploration dysfunctions of mice and it; exerts its effects perhaps by inhibiting AChE activity to reduce acetylcholine (ACh) hydrolysis in the brain and the serum in mice.

  • Design Space Exploration of a Reconfigurable HMAC-Hash Unit

    In this paper, a design space exploration of a reconfigurable HMAC-hash unit is discussed. This unit implements one of six standard hash algorithms, namely, MD5, SHA-1, RIPEMD-160, HMAC-MD5, HMAC-SHA-1, and HMAC-RIPEMD-160. The design space exploration of this unit is done using the Handel-C language. We propose key reuse mechanism for successive messages in order to improve the HMAC throughput. In addition, we explore the design space by providing two implementations of the HMAC algorithm, one for a general key size and another for a fixed key size. In each implementation, we use standard key use and the proposed key reuse mechanisms, and that results in four different implementations. The performance of these four implementations is analyzed with respect to three design metrics: area, delay, and throughput. We found that the proposed key reuse mechanism improves the HMAC throughput significantly when a large key is reused, with negligible increase in area and delay. In addition, we found that the implementation of HMAC for fixed key size is better in area, delay, and throughput than the HMAC implementation for general key size.

  • Novel Heuristic Mapping Algorithms for Design Space Exploration of Multiprocessor Embedded Architectures

    Electronic System level design has an important role in the multi-processor embedded system on chip design. Two important steps in this process are evaluation of a single design configuration and design space exploration. In the first part of design process, high-level simple analytical models for application mapping and evaluation are used and modified aiming at accelerating the evaluation of a single design configuration. Using the analytical model the design space is pruned and explored at high speed with low accuracy. In the second part of the design process, two Multi Objective Optimization Algorithms based on Particle Swarm Optimization and Simulated Annealing have been proposed to perform design space exploration of the pruned design space with higher accuracy taking advantages of low-level architectural simulation engines. The results obtained by proposed algorithms will provide the designer more accurate solutions within an acceptable time. Considering the MJPEG application as the case study, each of these methods produces a set of near-optimal points. Simulation results show that the proposed methods can lead to near-optimal design configurations with acceptable accuracy in reasonable time.

  • Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications

    Increasing diversity in packet-processing applications and rapid increases in channel bandwidth lead to greater complexity in communication protocols. These factors result in larger computational loads for packet-processing engines that introduce high performance microprocessor designs as an important solution. This paper presents an exhaustive simulation for exploring the performance of instruction-level parallel super scalar processors executing packet-processing applications. Based on the simulation results, a design space exploration has been used to derive performance-efficient application- specific super scalar processor architecture based on MIPS instruction set architecture. Simple Scalar architecture toolset has been used for design space exploration and network applications have been investigated to guide the architecture exploration. The optimizations achieve up to 80% improvement in performance for representative packet-processing applications.

  • Systems design space exploration by serial dataflow program execution

    The increasing ubiquity of heterogeneous parallel computing platforms nowadays creates the challenge to fully exploit the available computational power when porting existing programs or developing new applications with portability in mind. Existing design space exploration methods focus on specialized applications amenable to compile-time analysis. Real-world applications, however, tend to exhibit complex behavior that depends on input data and even timing. This paper proposes a methodology for creating a finite (approximate) representation of the design space of general streaming applications, based on detailed tracking of a serial run of the program. Homotopy theoretic methods are used to demonstrate how the design space of a program can be reconstructed from its serial execution trajectory. Moreover, the concept of a dependency graph of a dataflow program defined in the literature is extended with the definition of two new kinds of dependencies - the Guard Enable and Disable - and the 3-tuple notion needed to represent them.

  • A high reliability error control technique for deep space exploration

    Due to the large error correction capacity of stochastic and burst errors, Reed-Solomon codes are widely employed as error control codes in various occasions of uplink data control in deep space exploration. This paper investigates one of the decoding techniques of CCSDS RS (255, 223) code based on soft decision adaptive belief propagation algorithm. In order to reduce the complexities and improve decoding efficiency, an improved ABP algorithm with more inner BP iterations is proposed, which deduces the number of outer full iterations. Simulation results, by optimizing the number of outer iterations and inner iterations, show that, the proposed technique gains almost one times in decoding efficiency, while providing close decoding performance.

  • Fast and Energy-Driven Design Space Exploration for Heterogeneous Architectures

    In the last years, the integration of specialized hardware accelerators in Multiprocessor System-on-Chip (MpSoC) led to a new kind of architectures combining both software (SW) and hardware (HW) computational resources. For these new Heterogeneous MpSoC (HMpSoC) architectures, performance and energy consumption depend on a large set of parameters such as the HW/SW partitioning, the type of HW implementation or the communication cost. Design Space Exploration (DSE) consists in adjusting these parameters while monitoring a set of metrics (execution time, power, energy efficiency) to find the best mapping of the application on the targeted architecture. With the shift from performance-aware to energy-aware designs, computer-aided design and development tools try to reduce the large design space by simplifying HW/SW mapping mechanisms. However, energy consumption is not well supported in most of DSE tools due to the difficulty to fast and accurately estimate the energy consumption. To this aim, this work introduces a DSE method based on an analytical power model to circumvent the computation time bottleneck of state- of-the-art DSE methods. This exploration method proposes to optimize the HW/SW partitioning and mapping under user-defined objectives, especially an energy constraint. It targets tiling-based parallel applications and relies on an analytical power model that provides the DSE framework with the execution time and energy of a HW/SW configuration. The power model parameters are obtained with the measurements of a tiny subset of the design space, which are then injected into two extraction functions to obtain analytical formulations of the execution time and the energy consumption of the computation kernel. The partitioning problem constraints are defined as a set of inequalities with Boolean, integer (discrete) and non-integer (continuous) variables within a Mixed Integer Linear Programming (MILP) framework. Then, the best configuration that minimizes the user objective (e.g. execution time or total energy consumption) can be efficiently determined using commercial or open source solvers within a second. This methodology was tested on a Zynq-based heterogeneous architecture with two application kernels: a matrix multiplication and a Stencil computation. The results show a minimum of 12% acceleration speed-up and energy saving compared to standard approaches. They also show that the most energy-efficient solution is application-and platform- dependent and moreover hardly predictable. Such method could be included in a complete framework with a multi-step exploration to obtain an energy-efficient mapping of a full application on HMpSoC and to open new opportunity for future computer-aided design tools.

  • Accurate Analytical Spiral Inductor Modeling Techniques for Efficient Design Space Exploration

    Efficient modeling techniques are required to accelerate design space exploration for integrated spiral inductors. In this letter, closed-form modeling techniques for the inductor's physical inductance and substrate eddy currents are introduced. The model provides several orders of magnitude performance improvement over field-solver-based approaches with typical errors of less than 4% while demonstrating excellent agreement with measured data from fabricated inductors

  • Design space exploration of cache memory — A survey

    Cache memory plays a major role in memory hierarchy for improving the system performance. Cache configuration includes cache size, associativity, block size, replacement policy and write policies. Selection of different values for all these parameters decide the performance, energy consumption and chip area of the system for the given application. Finding the best cache configuration for application involves the cache design space exploration. Cache design space is time consuming because it contains all combination of cache parameters. This paper surveys different techniques to find the efficient design space aimed at reducing the design space time and provide good insight to researchers to explore further.



Standards related to Space Exploration

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Jobs related to Space Exploration

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