Conferences related to Pipeline

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2018 24th International Conference on Pattern Recognition (ICPR)

ICPR will be an international forum for discussions on recent advances in the fields of Pattern Recognition, Machine Learning and Computer Vision, and on applications of these technologies in various fields

  • 2016 23rd International Conference on Pattern Recognition (ICPR)

    ICPR'2016 will be an international forum for discussions on recent advances in the fields of Pattern Recognition, Machine Learning and Computer Vision, and on applications of these technologies in various fields.

  • 2014 22nd International Conference on Pattern Recognition (ICPR)

    ICPR 2014 will be an international forum for discussions on recent advances in the fields of Pattern Recognition; Machine Learning and Computer Vision; and on applications of these technologies in various fields.

  • 2012 21st International Conference on Pattern Recognition (ICPR)

    ICPR is the largest international conference which covers pattern recognition, computer vision, signal processing, and machine learning and their applications. This has been organized every two years by main sponsorship of IAPR, and has recently been with the technical sponsorship of IEEE-CS. The related research fields are also covered by many societies of IEEE including IEEE-CS, therefore the technical sponsorship of IEEE-CS will provide huge benefit to a lot of members of IEEE. Archiving into IEEE Xplore will also provide significant benefit to the all members of IEEE.

  • 2010 20th International Conference on Pattern Recognition (ICPR)

    ICPR 2010 will be an international forum for discussions on recent advances in the fields of Computer Vision; Pattern Recognition and Machine Learning; Signal, Speech, Image and Video Processing; Biometrics and Human Computer Interaction; Multimedia and Document Analysis, Processing and Retrieval; Medical Imaging and Visualization.

  • 2008 19th International Conferences on Pattern Recognition (ICPR)

    The ICPR 2008 will be an international forum for discussions on recent advances in the fields of Computer vision, Pattern recognition (theory, methods and algorithms), Image, speech and signal analysis, Multimedia and video analysis, Biometrics, Document analysis, and Bioinformatics and biomedical applications.

  • 2002 16th International Conference on Pattern Recognition


2018 IEEE Petroleum and Chemical Industry Technical Conference (PCIC)

The PCIC provides an international forum for the exchange of electrical applications technology related to the petroleum and chemical industry. The PCIC annual conference is rotated across North American locations of industry strength to attract national and international participation. User, manufacturer, consultant, and contractor participation is encouraged to strengthen the conference technical base. Success of the PCIC is built upon high quality papers, individual recognition, valued standards activities, mentoring, tutorials, networking, and conference sites that appeal to all.


2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

PRIME2017 conference program will reflect the wide spectrum of research topics in Microelectronics and Electronics, building bridges between various research fields. PRIME has been established over the recent years as an important conference where Ph.D. students and post-docs with less than one year post-Pd.D. experience can present their research results and network with experts from industry, academia and research. The main objectives of PRIME are: to encourage favourable exposure to Ph. D. students in the early stages of their careers; to benchmark Ph.D. research in a friendly and cooperative environment; to enable sharing of student and supervisor experiences of scientific and engineering research; to connect Ph.d. students and their supervisors with companies and research centres.

  • 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    PRIME2016 conference program will reflect the wide spectrum of research topics in Microelectronics and Electronics, building bridges between various research fields. PRIME has been established over the recent years as an important conference where PhD students and post-docs with less than one year post-PhD experience can present their research results and network with experts from industry, academia and research. The main objectives of PRIME are: to encourage favourable exposure to Ph.D. students in the early stages of their careers; to benchmark Ph.D. research in a friendly and cooperative environment; to enable sharing of student and supervisor experiences of scientific and engineering research; to connect Ph.D. students and their supervisors with companies and research centres.

  • 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    PRIME conference is dedicated to Ph. D. students who have to present all regular papers.The purpose of PRIME is to: Encourage favorable exposure to Ph. D. students in the early stage of their career, Benchmark Ph. D. research in a friendly and cooperative environment, Enable sharing of Ph. D. and supervisors experience on scientific research, Create a connection between academic world and companies to meet these expectations PRIME features: Conference program reflecting the wide spectrum of research topics in Microelectronics and Electronics, building bridges between research fields, Free of charge full-day tutorials for all conference participants, Company Fair for fruitful interactions between Ph.D. students and their supervisors with industry representatives

  • 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    PRIME conference is dedicated to Ph. D. students who have to present all regular papers.The purpose of PRIME is to :- Encourage favorable exposure to Ph. D. students in the early stage of their career- Benchmark Ph. D. research in a friendly and cooperative environment- Enable sharing of Ph. D. and supervisors experience on scientific research- Create a connection between academic world and companiesTo meet these expectations PRIME features:- Conference program reflecting the wide spectrum of research topics in Microelectronics and Electronics, building bridges between research fields- Free of charge full-day tutorials for all conference participants- Company Fair for fruitful interactions between Ph.D. students and their supervisors with industry representatives

  • 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    The conference is a meeting point for PhD students that have the opportunity to present their scientific activities.

  • 2012 8th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    Encourage publication by Ph.D. students in the early stages of their career, in order to benchmark there research in a friendly and cooperative environment. Enable sharing of scientific and engineering experiences between students and supervisors.

  • 2011 7th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    The objectives of PRIME are: - to encourage favourable exposure to Ph. D. students in the early stages of their careers; - to benchmark Ph.D. research in a friendly and cooperative environment; - to enable sharing of students and supervisors experiences of scientific and engineering research; - to connect Ph.D. students and their supervisors with companies and research centers.

  • 2010 Ph.D. Research in Microelectronics and Electronics (PRIME)

    Last year P.hD. candidates should be come together at PRIME 2010 to be networked with Industry

  • 2009 Ph.D. Research in Microelectronics and Electronics (PRIME)

    The objectives of PRIME are: to encourage favourable exposure to Ph.D. students in the early stages of their careers, to benchmark Ph.D. research in a friendly and cooperative environment, to enable sharing of students and supervisors experiences of scientific and engineering research, and to connect Ph.D. students and their supervisors with companies and research centres.

  • 2008 Ph.D. Research in Microelectronics and Electronics (PRIME)

    The purpose of this conference is to: # Encourage favourable exposure to Ph.D. students in the early stage of their career # Benchmark Ph.D. research in a friendly and cooperative environement # Enable sharing of Ph.D. and supervisors experience on scientific research # Create at the Company Fair a connection between academic world (Ph.D. students) and companies The aim of PRIME 2008 is to provide an opportunity for Ph.D. students to present their research activity and contact other people in the rese

  • 2007 Ph.D. Research in Microelectronics and Electronics (PRIME)

    The purpose of this conference is to encourage favourable exposure to Ph.D. students in the early stage of their career and to benchmark Ph.D. research in a friendly and cooperative environment. It will also enable sharing of Ph.D. and supervisors experience on scientific research and create at the Company Fair a connection between academic world (Ph.D. students) and companies.

  • 2006 Ph.D. Research in Microelectronics and Electronics (PRIME)

  • 2005 Ph.D. Research in Microelectronics and Electronics (PRIME)


2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

SMACD is a dedicated forum devoted to Design Methods and Tools for Analog, Mixed-signal, RF (AMS/RF) and multi-domain (MEMs, nanoelectronic, optoelectronic, biological, etc.) integrated circuits and systems.


2017 27th International Conference on Field Programmable Logic and Applications (FPL)

The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing. The conference objective is to bring together researchers and practitioners from both academia and industry and from around the world. FPL 2017 will offer the following five conference tracks: Architectures and Technology; Applications and Benchmarks; Design Methods and Tools; Self-aware and Adaptive Systems; Surveys, Trends and Education.

  • 2016 26th International Conference on Field Programmable Logic and Applications (FPL)

    The International Conference on Field Programmable Logic and Applications (FPL) is the firstand largest conference covering the rapidly growing area of field-programmable logic. Duringthe past 26 years, many of the advances achieved in reconfigurable system architectures,applications, embedded processors, design automation methods (EDA) and tools have beenfirst published in the proceedings of the FPL conference series. FPL 2016 will offer the followingfive conference tracks: Architectures and Technology, Applications and Benchmarks, DesignMethods and Tools, Self-aware and Adaptive Systems, Surveys, Trends and Education

  • 2015 25th International Conference on Field Programmable Logic and Applications (FPL)

    The International Conference on Field Programmable Logic and Applications (FPL) is the first and largest conference covering the rapidly growing area of field-programmable logic. During the past 25 years, many of the advances achieved in reconfigurable system architectures, applications, embedded processors, design automation methods (EDA) and tools have been first published in the proceedings of the FPL conference series. FPL 2015 plans to gear a technical focus towards: “Power efficient and self-aware FPGA accelerators and heterogeneous computing platforms for HPC and embedded / cyber physical systems”. Highlights of FPL 2015 will include industry keynotes. FPL 2015 will offer the following five conference tracks: Architectures and Technology, Applications and Benchmarks, Design Methods and Tools, Self-aware and Adaptive Systems, Surveys, Trends and Education

  • 2014 24th International Conference on Field Programmable Logic and Applications (FPL)

    The International Conference on Field Programmable Logic and Applications (FPL) is the first and largest conference covering the rapidly growing area of field-programmable logic. During the past 23 years, many of the advances achieved in reconfigurable system architectures, applications, embedded processors, design automation methods (EDA) and tools have been first published in the proceedings of the FPL conference series. Its objective is to bring together researchers and practitioners from both academia and industry from all over the world.A special focus for FPL 2014 shall be on dependable, power efficient FPGA accelerators and heterogeneous computing platforms for HPC and embedded / cyber physical systems. Submissions shall be categorized into the following four tracks: Architectures and Technology, Applications and Benchmarks, Design Methods and Tools, Surveys, Trends and Education.

  • 2013 23rd International Conference on Field Programmable Logic and Applications (FPL)

    The objective of FPL is to bring together researchers and industry from all over the world for a wide ranging discussion on FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration.The conference topics include, but are not limited to: Architectures; Design Methods and Tools; Applications (aerospace and automotive, bioinformatics, finance, medical, security); Surveys, Trends and Education.

  • 2012 22nd International Conference on Field Programmable Logic and Applications (FPL)

    Applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration of field programmable logic.

  • 2011 International Conference on Field Programmable Logic and Applications (FPL)

    FPL is the first and largest conference covering the rapidly growing area of field-programmable logic. Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion on FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration.

  • 2010 International Conference on Field Programmable Logic and Applications (FPL)

    The conference objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs and other field-programmable devices, their architectures and design methods, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2009 International Conference on Field Programmable Logic and Applications (FPL)

    The conference objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs and other field-programmable devices, their architectures and design methods, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2008 International Conference on Field Programmable Logic and Applications (FPL)

    Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2007 International Conference on Field Programmable Logic and Applications (FPL)

    Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2006 International Conference on Field Programmable Logic and Applications (FPL)

  • 2005 International Conference on Field Programmable Logic and Applications (FPL)


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Periodicals related to Pipeline

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems Magazine, IEEE


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


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Xplore Articles related to Pipeline

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L-infinite Coding of 3D Representations of Human Affect

Ruxandra Florea; Leon Denis; Jan Lievens; Peter Schelkens; Adrian Munteanu 2012 IEEE International Conference on Multimedia and Expo Workshops, 2012

Off-line scanning, coding, transmission and remote animation of the human affect represents a possible processing pipeline for providing 3D immersion in virtual worlds. In this paper we target applications that make use of compact and scalable 3D representations of human affect and require close control over the local error introduced by lossy coding of the mesh geometry. To satisfy this ...


Pipelined architecture for FPGA implementation of lifting-based DWT

Zhigang Wu; Wei Wang 2011 International Conference on Electric Information and Control Engineering, 2011

This paper presents a high speed 9/7 lifting 1D-DWT algorithm which is implementation on FPGA with multi-stage pipelining structure. Compared with the architecture which without multi-stage pipeline, the proposed architecture has higher operating frequency, the design raises operating frequency around 1.5 times more fast, at the expense of about 27% more hardware area. The hardware architecture is suitable for high ...


A modular systolic architecture for delayed least mean squares adaptive filtering

V. Visvanathan; N. Ramanathan Proceedings of the 8th International Conference on VLSI Design, 1995

Existing systolic architectures for DLMS adaptive filtering, delay the coefficient adaptation by (N-1) or N input sampling periods for a filter of order N. Further, these architectures enforce an output latency of the same amount, which translates to a tracking delay. Using an alternate systolization technique, this paper presents a systolic DLMS adaptive filter architecture in which the need for ...


Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems

Yuliang Tao; Guanghui He; Weifeng He; Qin Wang; Jun Ma; Zhigang Mao 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011

Reconfigurable computing arrays facilitate the flexibility with high performance for regular and computation-intensive algorithms in multimedia processing. However, the efficiency of the irregular and control-intensive algorithms becomes the performance bottleneck of reconfigurable multimedia systems. In this paper, we propose the design and VLSI implementation of a novel memory efficient macroblock prediction and boundary strength (Bs) calculation engine. The control-intensive algorithms, ...


Design on Parallel Structure of DSSS Receiver Using FPGA

Jie Yang; Qian Zhu 2010 6th International Conference on Wireless Communications Networking and Mobile Computing (WiCOM), 2010

In this paper, a novel high-speed parallel structure of low-pass filter for filtering and matched algorithm for searching synchronization in DSSS receiver is studied. We extend previous implements for introducing parallelism into the design of Direct Sequence Spread Spectrum (DSSS) receiver. Design techniques, such as parallel structure, optimized compressor cells and pipeline architecture for reducing the hardware resource consumption of ...


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Educational Resources on Pipeline

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eLearning

L-infinite Coding of 3D Representations of Human Affect

Ruxandra Florea; Leon Denis; Jan Lievens; Peter Schelkens; Adrian Munteanu 2012 IEEE International Conference on Multimedia and Expo Workshops, 2012

Off-line scanning, coding, transmission and remote animation of the human affect represents a possible processing pipeline for providing 3D immersion in virtual worlds. In this paper we target applications that make use of compact and scalable 3D representations of human affect and require close control over the local error introduced by lossy coding of the mesh geometry. To satisfy this ...


Pipelined architecture for FPGA implementation of lifting-based DWT

Zhigang Wu; Wei Wang 2011 International Conference on Electric Information and Control Engineering, 2011

This paper presents a high speed 9/7 lifting 1D-DWT algorithm which is implementation on FPGA with multi-stage pipelining structure. Compared with the architecture which without multi-stage pipeline, the proposed architecture has higher operating frequency, the design raises operating frequency around 1.5 times more fast, at the expense of about 27% more hardware area. The hardware architecture is suitable for high ...


A modular systolic architecture for delayed least mean squares adaptive filtering

V. Visvanathan; N. Ramanathan Proceedings of the 8th International Conference on VLSI Design, 1995

Existing systolic architectures for DLMS adaptive filtering, delay the coefficient adaptation by (N-1) or N input sampling periods for a filter of order N. Further, these architectures enforce an output latency of the same amount, which translates to a tracking delay. Using an alternate systolization technique, this paper presents a systolic DLMS adaptive filter architecture in which the need for ...


Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems

Yuliang Tao; Guanghui He; Weifeng He; Qin Wang; Jun Ma; Zhigang Mao 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011

Reconfigurable computing arrays facilitate the flexibility with high performance for regular and computation-intensive algorithms in multimedia processing. However, the efficiency of the irregular and control-intensive algorithms becomes the performance bottleneck of reconfigurable multimedia systems. In this paper, we propose the design and VLSI implementation of a novel memory efficient macroblock prediction and boundary strength (Bs) calculation engine. The control-intensive algorithms, ...


Design on Parallel Structure of DSSS Receiver Using FPGA

Jie Yang; Qian Zhu 2010 6th International Conference on Wireless Communications Networking and Mobile Computing (WiCOM), 2010

In this paper, a novel high-speed parallel structure of low-pass filter for filtering and matched algorithm for searching synchronization in DSSS receiver is studied. We extend previous implements for introducing parallelism into the design of Direct Sequence Spread Spectrum (DSSS) receiver. Design techniques, such as parallel structure, optimized compressor cells and pipeline architecture for reducing the hardware resource consumption of ...


More eLearning Resources

IEEE-USA E-Books

  • Dedicated and Programmable Digital Signal Processors

    This chapter contains sections titled: A Low-Power Chipset for a Portable Multimedia I/O Terminal A Portable Real-Time Video Decoder for Wireless Communication Low Power Design of Memory Intensive Functions A 16b Low-Power Digital Signal Processor A 1.8V 36mW DSP for the Half-Rate Speech CODEC Design of a 1-V Programmable DSP for Wireless Communication Stage-Skip Pipeline: A Low Power Processor Architecture Using a Decoded Instruction Buffer

  • Introduction to 3D Graphics

    This chapter contains sections titled: The 3D Graphics Pipeline Programmable 3D Graphics References

  • No title

    This book presents techniques to render photo-realistic images by programming the Graphics Processing Unit (GPU). We discuss effects such as mirror reflections, refractions, caustics, diffuse or glossy indirect illumination, radiosity, single or multiple scattering in participating media, tone reproduction, glow, and depth of field. The book targets game developers, graphics programmers, and also students with some basic understanding of computer graphics algorithms, rendering APIs like Direct3D or OpenGL, and shader programming. In order to make the book self-contained, the most important concepts of local illumination and global illumination rendering, graphics hardware, and Direct3D/HLSL programming are reviewed in the first chapters. After these introductory chapters we warm up with simple methods including shadow and environment mapping, then we move on toward advanced concepts aiming at global illumination rendering. Since it would have been impossible to give a rigorous review f all approaches proposed in this field, we go into the details of just a few methods solving each particular global illumination effect. However, a short discussion of the state of the art and links to the bibliography are also provided to refer the interested reader to techniques that are not detailed in this book. The implementation of the selected methods is also presented in HLSL, and we discuss their observed performance, merits, and disadvantages. In the last chapter, we also review how these techniques can be integrated in an advanced game engine and present case studies of their exploitation in games. Having gone through this book, the reader will have an overview of the state of the art, will be able to apply and improve these techniques, and most importantly, will be capable of developing brand new GPU algorithms. Table of Contents: Global Illumintation Rendering / Local Illumination Rendering Pipeline of GPUs / Programming and Controlling GPUs / Simple Improvements of the ocal Illumination Model / Ray Casting on the GPU / Specular Effects with Rasterization / Diffuse and Glossy Indirect Illumination / Pre-computation Aided Global Illumination / Participating Media Rendering / Fake Global Illumination / Postprocessing Effects / Integrating GI Effects in Games and Virtual Reality Systems / Bibliography

  • No title

    Geometric programming is used for design and cost optimization and the development of generalized design relationships and cost rations for specific problems. The early pioneers of the process, Zener, Duffin, Peterson, Beightler, and Wilde, played important roles in the development of geometric programming. The theory of geometric programming is presented and 10 examples are presented and solved in detail. The examples illustrate some of the difficulties encountered in typical problems and techniques for overcoming these difficulties. The primal-dual relationships are used to illustrate how to determine the primal variables from the dual solution. These primal-dual relationships can be used to determine additional dual equations when the degrees of difficulty are positive. The goal of this work is to have readers develop more case studies to further the application of this exciting mathematical tool. Table of Contents: Introduction / Brief History of Geometric Programming / Theoretica Considerations / Trash Can Case Study / Open Cargo Shipping Box Case Study / Metal Casting Cylindrical Riser Case Study / Process Furnace Design Case Study / Gas Transmission Pipeline Case Study / Journal Bearing Design Case Study / Metal Casting Hemispherical Top Cylindrical Side Riser / Liquefied Petroleum Gas(LPG) Cylinders Case Study / Material Removal/Metal Cutting Economics Case Study / Summary and Future Directions

  • Architecting Area

    This chapter contains sections titled: Rolling Up the Pipeline Control-Based Logic Reuse Resource Sharing Impact of Reset on Area Summary of Key Points

  • Camera-Based Image Forgery Detection

    Recently, an increased number of studies in image authentication and image forgery detection have appeared that are based on indicators arising from the acquisition process of the data, namely due to the inherent characteristics of the camera used to produce the image. This chapter focuses on different aspects of image forgery based on effects and cues found in the image that are due to the acquisition process. These aspects include: image authentication, image forgery detection and image signature. These studies are termed as camera-based image forgery detection methods. The chapter describes the camera structure and the three major components: optics, sensors and imaging pipeline. For each component, its basic mechanism, its role in the acquisition process and its effects on the final acquired image are detailed. The chapter presents a specific camera-based image forgery technique as a case study for the approaches.

  • Recognition and Pose Estimation of Rigid Transparent Objects with a Kinect Sensor

    Recognizing and determining the 6DOF pose of transparent objects is necessary in order for robots to manipulate such objects. However, it is a challenging problem for computer vision. We propose new algorithms for segmentation, pose estimation and recognition of transparent objects from a single RGB-D image from a Kinect sensor. Kinect's weakness in the perception of transparent objects is exploited in their segmentation. Following segmentation, edge fitting is used for recognition and pose estimation. A 3D model of the object is created automatically during training and it is required for pose estimation and recognition. The algorithm is evaluated in different conditions of a domestic environment within the framework of a robotic grasping pipeline where it demonstrates high grasping success rates compared to the state-of- the-art results. The method doesn't deal with occlusions and overlapping transparent objects currently but it is robust against non-transparent clutter.

  • Lying Pose Recognition for Elderly Fall Detection

    This paper proposes a pipeline for lying pose recognition from single images, which is designed for health-care robots to find fallen people. We firstly detect object bounding boxes by a mixture of viewpoint-specific part based model detectors and later estimate a detailed configuration of body parts on the detected regions by a finer tree-structured model. Moreover, we exploit the information provided by detection to infer a reasonable limb prior for the pose estimation stage. Additional robustness is achieved by integrating a viewpoint-specific foreground segmentation into the detection and body pose estimation stages. This step yields a refinement of detection scores and a better color model to initialize pose estimation. We apply our proposed approach to challenging data sets of fallen people in different scenarios. Our quantitative and qualitative results demonstrate that the part-based model significantly outperforms a holistic model based on same feature type for lying pose detection. Moreover, our system offers a reasonable estimation for the body configuration of varying lying poses.

  • No title

    As new displays and cameras offer enhanced color capabilities, there is a need to extend the precision of digital content. High Dynamic Range (HDR) imaging encodes images and video with higher than normal 8 bit-per-color-channel precision, enabling representation of the complete color gamut and the full visible range of luminance.However, to realize transition from the traditional toHDRimaging, it is necessary to develop imaging algorithms that work with the high-precision data. Tomake such algorithms effective and feasible in practice, it is necessary to take advantage of the limitations of the human visual system by aligning the data shortcomings to those of the human eye, thus limiting storage and processing precision. Therefore, human visual perception is the key component of the solutions we discuss in this book. This book presents a complete pipeline forHDR image and video processing fromacquisition, through compression and quality evaluation, to display. At the HDR image and vi eo acquisition stage specialized HDR sensors or multi- exposure techniques suitable for traditional cameras are discussed. Then, we present a practical solution for pixel values calibration in terms of photometric or radiometric quantities, which are required in some technically oriented applications. Also, we cover the problem of efficient image and video compression and encoding either for storage or transmission purposes, including the aspect of backward compatibility with existing formats. Finally, we review existing HDR display technologies and the associated problems of image contrast and brightness adjustment. For this purpose tone mapping is employed to accommodate HDR content to LDR devices. Conversely, the so-called inverse tone mapping is required to upgrade LDR content for displaying on HDR devices. We overview HDR-enabled image and video quality metrics, which are needed to verify algorithms at all stages of the pipeline. Additionally, we cover successful examples of the H R technology applications, in particular, in computer graphics and computer vision. The goal of this book is to present all discussed components of the HDR pipeline with the main focus on video. For some pipeline stages HDR video solutions are either not well established or do not exist at all, in which case we describe techniques for single HDR images. In such cases we attempt to select the techniques, which can be extended into temporal domain. Whenever needed, relevant background information on human perception is given, which enables better understanding of the design choices behind the discussed algorithms and HDR equipment. Table of Contents: Introduction / Representation of an HDR Image / HDR Image and Video Acquisition / HDR Image Quality / HDR Image, Video, and Texture Compression / Tone Reproduction / HDR Display Devices / LDR2HDR: Recovering Dynamic Range in Legacy Content / HDRI in Computer Graphics / Software

  • Drowning in the Sink-or-Swim Economy

    This chapter contains sections titled: Volatile Continuity in the Information Economy, Topographies of Inequality in Troy, Has the Information Economy Arrived in the Capital Region?, Does the Rising Tide Lift All Boats?, Already Here, Increasingly Vulnerable, Holding Up the Pipeline, High-Tech Development in an Unflat World



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