Conferences related to Network-on-chip

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2018 IEEE Seventh International Conference on Communications and Electronics (ICCE)

communications and electronics

  • 2016 IEEE Sixth International Conference on Communications and Electronics (ICCE)

    Contributed papers are solicited describing original works in electronics, communications engineering and related technologies. Topics and technical areas of interest include but are not limited to the following: 1. Communications Networks and Systems; 2. Signal Processing and Applications; 3. Microwave Engineering; 4. Electronics Systems. In addition, three special sessions are included in the scope of ICCE2016: 1. Software Defined Networking 2.Underwater Acoustic Communication3.Crowdsourcing and Crowdsourcing Application

  • 2014 IEEE Fifth International Conference on Communications and Electronics (ICCE)

    Contributed papers are solicited describing original works in electronics, communications engineering and related technologies. Topics and technical areas of interest include but are not limited to the following: Communications Networks & Systems; Signal Processing and Applications; Microwave Engineering; Electronics Systems; with 3 special sessions on: Software Defined Networking; Underwater Acoustic Communications; Crowdsourcing.

  • 2012 Fourth International Conference on Communications and Electronics (ICCE)

    ICCE 2012 looks for significant contributions to various topics in communication engineering, networking, microwave engineering, signal processing and electronics engineering. The conference will also include tutorials, workshops, and technology panels given by world-class speakers.

  • 2010 Third International Conference on Communications and Electronics (ICCE)

    ICCE 2010 will focus on cutting edge research, development, and applications of communications and electronics technologies, and aims at continuing and accelerating the momentum of researching in electronics and telecommunications areas. ICCE 2010 will also provide the best and most current tutorials, research results, industry-oriented technical contents, thereby facilitating scientific idea exchange and the identification and definition of future trends and directions on these fields.

  • 2008 Second International Conference on Communications and Electronics (ICCE)

    The Second International Conference on Communications and Electronics (ICCE 2008) is devoted to the research, development, and application of communications and electronics technologies, and aims at continuing and accelerating the momentum of researching in telecommunication areas.

  • 2006 First International Conference on Communications and Electronics (ICCE)


2017 12th IEEE International Symposium onIndustrial Embedded Systems (SIES)

Recent developments, deployments, technology trends and research results, as well as initiatives related to embedded systems and their applications in a variety of industrial environments.


2017 12th International Conference on Computer Engineering and Systems (ICCES)

Computer Engineering and Systems


2017 14th International Conference The Experience of Designing and Application of CAD Systems in Microelectronics (CADSM)

Modeling and simulation of hydro- and gasodynamic processes. New materials in microelectronics. New technology of IC and MEMS industry. Practical realization and industrial application. Problems of technological processes testing. Problems of reliability estimation.Signal processing in radioelectronic systems and telecommunications. Telecommunications and radioelectronic design tools. Electronic and computer tools in biomedical engineering. Methods and tools of digital signal processing.Specialized computer system. Computer system and networks. Data and knowledge bases. Design of MEMS elements. CAD systems for MEMS design.Problemss of optimal design. Object-oriented design methods. Combinatorial and graph tasks of huge size. Constructor design of radioelectronic means. Design solving verification. Thermal problems in microelectronics.Mathematical model of sensors and actuators. Microsystems modeling and design. New microelectronic technologies.


2017 14th International Multi-Conference on Systems, Signals & Devices (SSD)

The International Multi-Conference on Systems, Signals and Devices 2017 is a forum for researchers and specialists in different fields of electrical engineering departments from leading research centers and universities around the world to present their research results and to share experiences with other attendees. On behalf of International Multi-Conference on Systems, Signals & Devices Organizing Committee, it is our great pleasure to extend a warm invitation to you to participate in SSD'17. Since 2001, SSD has grown substantially from a brand new conference with a strong vision to the SSD of today, dedicated to the advancement of electrical engineering research fields and their practice.

  • 2016 13th International Multi-Conference on Systems, Signals & Devices (SSD)

    SSD is a renowned scientic event that includes five scheduled conferences covering almost allfields of electrical and electronics engineeringnamely: Systems Automation and Controls (SAC), Communication, Signal Processing & Information Technologies (CSP), Sensors, Circuits and Instrumentation Systems (SCI), Micro and Nano Electronic Systems (MiNE) and Power Systems and Smart Energies (PSE).The event is a forum for researchers and practitioners to discuss the latest findings in electricaland electronics engineering research. It provides a serious opportunity for participants to promote networking between scientists and universities.

  • 2015 12th International Multi-Conference on Systems, Signals & Devices (SSD)

    SSD is a renowned scientic event that includes five scheduled conferences covering almost all fields of electrical and electronics engineeringnamely: Systems Analysis and Automatic Control (SAC), Power Electrical Systems (PES), Communication and Signal Processing (CSP), Sensors, Circuits andInstrumentation Systems (SCI), Computers & Information Technology (CIT).The event is a forum for researchers and practitioners to discuss the latest findings in electrical and electronics engineering research. It provides a seriousopportunity for participants to promote networking between scientists and universities.

  • 2014 11th International Multi-Conference on Systems, Signals & Devices (SSD)

    The International Multi-Conference on Systems, Signals and Devices 2014 is a forum for researchers and specialists in different fields of electrical engineering departments from leading research centers and universities around the world to present their research results and to share experiences with other attendees. SSD14 has four main topics: i) System Analysis and Automatic Control, ii) Power Electrical Systems, iii) Communication and Signal Processing, and iv) Sensors Circuits and Instrumentation Systems. The conference combines plenary sessions, keynote talks, academic presentations, discussion forums and academic-industry interaction.

  • 2013 10th International Multi-Conference onSystems, Signals & Devices (SSD)

    The 2013 International Multi-Conference on Systems, Signals and Devices is a forum for researchers and specialists in different fields of electrical engineering departments from leading research centers and universities around the world to present their research results and to share experiences with other attendees. It is the 10th multi -conference since the founding of SSD in 2001 whichis supported by international organizations such as IEEE, TSS and different scientific journals.

  • 2012 IEEE 9th International Multi-Conference on Systems, Signals and Devices (SSD)

    The International Multi-Conference on Systems, Signals and Devices 2012 is a forum for researchers and specialists in different fields of electrical engineering departments from leading reserach centers and universities around the world to present their research results and to share experiences with other attendees. It is the 9th multi-conference since the founding of SSD in 2001 which is supported by international organizations such as IEEE, TSS and different scientific journals.

  • 2011 8th International Multi-Conference on Systems, Signals and Devices (SSD)

    The SSD conference is a multi conference covering most topics in the the field of electrical engineering. It is celebrations its tenth birth day in 2011.

  • 2010 7th International Multi-Conference on Systems, Signals and Devices (SSD)

    The event consists of four specialized conferences that cover a wide spectrum of fields in electrical and electronics engineering and as follows Systems Analysis and Automatic Control Power Electrical Systems Communication and Signal Processing Sensors, Circuits and Instrumentation Systems

  • 2009 6th International Multi-Conference on Systems, Signals and Devices (SSD)

    The International Conference SSD 09 is a forum for specialists to present their research results and to share experiences with other attendees coming from all over the world. It is the 6th conference since the founding of SSD in 2001. SSD is supported by international organizations such as IEEE, TSS and different scientific journals. SSD 09 includes keynote lectures by eminent scientists as well as oral and poster sessions. All papers are peer reviewed on the basis of full manuscripts. SSD participants hav

  • 2008 5th International Multi-Conference on Systems, Signals and Devices (SSD)

    The International Multi-Conference on Systems signals & Devices is an annual scientific event that includes four scheduled conferences covering almost fields of electrical and electronics engineering: (1)Systems Analysis and Automatic Control, (2)Power Electrical Systems, (3)Communication and Signal Processing (4)Sensors, Circuits and Instrumentation Systems.


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Periodicals related to Network-on-chip

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Circuits and Systems Magazine, IEEE


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Dependable and Secure Computing, IEEE Transactions on

The purpose of TDSC is to publish papers in dependability and security, including the joint consideration of these issues and their interplay with system performance. These areas include but are not limited to: System Design: architecture for secure and fault-tolerant systems; trusted/survivable computing; intrusion and error tolerance, detection and recovery; fault- and intrusion-tolerant middleware; firewall and network technologies; system management ...


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Xplore Articles related to Network-on-chip

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QBLESS: A case for QoS-aware bufferless NoCs

Zhicheng Yao; Xiufeng Sui; Tianni Xu; Jiuyue Ma; Juan Fang; Sally A. McKee; Binzhang Fu; Yungang Bao 2014 IEEE 22nd International Symposium of Quality of Service (IWQoS), 2014

Datacenters consolidate diverse applications to improve utilization. However when multiple applications are co-located on such platforms, contention for shared resources like Networks-on-Chip (NoCs) can degrade the performance of latency-critical online services (high-priority applications). Recently proposed bufferless NoCs have the advantages of requiring less area and power, but they pose challenges in quality-of-service (QoS) support, which usually relies on buffer-based virtual ...


A General Fault-Tolerant Minimal Routing for Mesh Architectures

Hongzhi Zhao; Nader Bagherzadeh; Jie Wu IEEE Transactions on Computers, 2017

Fault-tolerant minimal routing algorithms aim at finding a Manhattan path between the source and destination nodes and route around all faulty nodes. Additionally, some non-faulty nodes that are helpless to make up of a fault- tolerant minimal path should also be routed around. How to label such non- faulty nodes efficiently is a major challenge. State-of-the-art solutions could not address ...


Topology generation and floorplanning for low power application-specific Network-on-Chips

Wan-Yu Lee; Iris Hui-Ru Jiang 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2008

Into the nanometer era, the number of cores and the amount of communication on a chip are rapidly increasing. Network-on-Chip can offer high communication efficiency, especially suitable for nanometer designs. Power and timing of low power application-specific Network- on-Chips dominate the system performance and highly depend on how the network topology connects routers and how many routers are used; area ...


Evaluation of Memory Access Arbitration Algorithm on Tilera's TILEPro64 Platform

Mayank Shekhar; Harini Ramaprasad; Frank Mueller 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems, 2015

As real-time embedded systems demand more and more computing power under reasonable energy budgets, multi-core platforms are a viable option. However, deploying real-time applications on multi-core platforms introduce several predictability challenges. One of these challenges is bounding the latency of memory accesses issued by real-time tasks. This challenge is exacerbated as the number of cores and, hence, the degree of ...


Application-specific memory performance of a heterogeneous reconfigurable architecture

Sean Whitty; Henning Sahlbach; Brady Hurlburt; Rolf Ernst; Wolfram Putzke-Röming 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010

Heterogeneous reconfigurable processing architectures are often limited by the speed at which they can access data in external memory. Such architectures are designed for flexibility to support a broad range of target applications, including advanced algorithms with significant processing and data requirements. Clearly, strong performance of applications in this category is an extremely relevant metric for demonstrating the full performance ...


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Educational Resources on Network-on-chip

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eLearning

QBLESS: A case for QoS-aware bufferless NoCs

Zhicheng Yao; Xiufeng Sui; Tianni Xu; Jiuyue Ma; Juan Fang; Sally A. McKee; Binzhang Fu; Yungang Bao 2014 IEEE 22nd International Symposium of Quality of Service (IWQoS), 2014

Datacenters consolidate diverse applications to improve utilization. However when multiple applications are co-located on such platforms, contention for shared resources like Networks-on-Chip (NoCs) can degrade the performance of latency-critical online services (high-priority applications). Recently proposed bufferless NoCs have the advantages of requiring less area and power, but they pose challenges in quality-of-service (QoS) support, which usually relies on buffer-based virtual ...


A General Fault-Tolerant Minimal Routing for Mesh Architectures

Hongzhi Zhao; Nader Bagherzadeh; Jie Wu IEEE Transactions on Computers, 2017

Fault-tolerant minimal routing algorithms aim at finding a Manhattan path between the source and destination nodes and route around all faulty nodes. Additionally, some non-faulty nodes that are helpless to make up of a fault- tolerant minimal path should also be routed around. How to label such non- faulty nodes efficiently is a major challenge. State-of-the-art solutions could not address ...


Topology generation and floorplanning for low power application-specific Network-on-Chips

Wan-Yu Lee; Iris Hui-Ru Jiang 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2008

Into the nanometer era, the number of cores and the amount of communication on a chip are rapidly increasing. Network-on-Chip can offer high communication efficiency, especially suitable for nanometer designs. Power and timing of low power application-specific Network- on-Chips dominate the system performance and highly depend on how the network topology connects routers and how many routers are used; area ...


Evaluation of Memory Access Arbitration Algorithm on Tilera's TILEPro64 Platform

Mayank Shekhar; Harini Ramaprasad; Frank Mueller 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems, 2015

As real-time embedded systems demand more and more computing power under reasonable energy budgets, multi-core platforms are a viable option. However, deploying real-time applications on multi-core platforms introduce several predictability challenges. One of these challenges is bounding the latency of memory accesses issued by real-time tasks. This challenge is exacerbated as the number of cores and, hence, the degree of ...


Application-specific memory performance of a heterogeneous reconfigurable architecture

Sean Whitty; Henning Sahlbach; Brady Hurlburt; Rolf Ernst; Wolfram Putzke-Röming 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010

Heterogeneous reconfigurable processing architectures are often limited by the speed at which they can access data in external memory. Such architectures are designed for flexibility to support a broad range of target applications, including advanced algorithms with significant processing and data requirements. Clearly, strong performance of applications in this category is an extremely relevant metric for demonstrating the full performance ...


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IEEE.tv Videos

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IEEE-USA E-Books

  • Time-Average-Frequency and Special Clocking Techniques: Gapped Clock, Stretchable Clock, and Pausible Clock

    Gapped clocking is a commonly used technique in optical transport networks (OTNs), broadcast video, and other applications. This chapter discusses the stretchable and pausible clock in connection with the application environment of a NoC (network-on-chip). The gapped clock is produced by removing pulses from a clock signal generated by an untouchable clock source. The chapter also discusses the techniques, including the gapped clock, stretchable clock, pausible clock, and possible others all have the Time-Average-Frequency (TAF) concept work behind the scene. All these special clocking techniques illustrate the fact that the essence of clock frequency is the accomplishment of a specified number of operations within the time window of 1 s. An important topic related to the gapped clock, pausible clock, and stretched clock is clock jitter. It is crucial to understand that the pulse-length modification introduced by these special clocking techniques is an intended operation.

  • Application Platform

    This chapter contains sections titled: * SoC Design Paradigms * System Architecture * Low-power SoC Design * Network-on-Chip based SoC * References

  • A Reconfigurable On-Chip Interconnection Network for Large Multicore Systems

    This chapter introduces the baseline reconfigurable networks-on-chip (NoC) architecture. It addresses two problems of core to network mapping and topology exploration in which the cores of a given set of input applications are physically mapped to the network and then a suitable topology is found for each individual application. Experimental results, using some multicore system-on-chips (SoC) workloads, show that this architecture effectively improves the performance of NoCs by 29% and reduces the power consumption by 9% over one of the most efficient and popular mapping algorithms proposed for conventional NoCs. The chapter extends the baseline reconfigurable NoC to a generalized reconfigurable NoC architecture. This new cluster-based structure consists of several mesh clusters alongside a reconfigurable connection fabric that handles the intercluster communication. It can support both local and global traffic patterns in an efficient manner.



Standards related to Network-on-chip

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