Conferences related to Network-on-chip

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2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)

NEWCAS2018 will encompass a wide range of special sessions and keynote talks given by prominent expertscovering key areas of research in microsystems in order to provide all attendees a unique forum for the exchange of ideas and results. The program of the conference will be tailored to reflect the wide spectrum of topics and research interest shared by researchers in this field.

  • 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)

    IEEE International NEWCAS Conference is tailored to reflect the wide spectrum of topics and research interests shared among the organizing entities. This collaboration will be oriented towards advanced research and development activities from academia, research institutions, and industry. Topics include, but are not limited to analog, mixed-signal, and digital integrated circuits and systems, radio-frequency circuits, computer architecture and memories, microsystems, sensors and actuators, test and verification, telecommunication, technology trends, power and energy circuits and systems, biomedical circuits, energy harvesting, computer-aided design tools, device modeling, and embedded portable devices.

  • 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)

    IEEE International NEWCAS Conference is tailored to reflect the wide spectrum of topics and research interests shared among the organizing entities. This collaboration will be oriented towards advanced research and development activities from academia, research institutions, and industry. Topics include, but are not limited to analog, mixed-signal, and digital integrated circuits and systems, radio-frequqncy circuits, computer architecture and memories, microsystems, sensors and actuators, test and verification, telecommunication, technology trends, power and energy circuits and systems, biomedical circuits, energy harvesting, computer-aided design tools, and embedded portable devices.

  • 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)

    The program of the conference will be tailored to reflect the wide spectrum of topics and research interest shared among the organizing entities. This collaboration will be oriented towards advanced research in adaptive systems which constitutes the highlights of the NEWCAS conference, but also areas related to analog and digital signal processing, low power consumption, and circuits and systems designs. The topics include, but are not limited to: Computer architecture and memories, Analog circuit design, Digital and mixed-signal circuit design, RF circuit design, Microsystems, sensors and actuators, Test and verification, Telecom, microwaves and RF, Technology Trends, Data and signal processing, Neural networks and artificial vision, CAD and design tools, Low-Power circ. & syst. techniques, Imaging & image sensors, Embedded hand-held devices, Biomed. circuits & systems, Energy Harvesting / Scavenging

  • 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

    will encompass a wide range of special sessions and keynote talks given by prominent experts covering key areas of research in microsystems in order to provide all attendees a unique forum for the exchange of ideas and results. The program of the conference will be tailored to reflect the wide spectrum of topics and research interest shared by researchers in this field.

  • 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

    NEWCAS is a major international conference presenting design methodologies, techniques and experimental results in emerging electronics, circuits and systems topics. The NEWCAS conference deals with analog and digital signal processing, low power consumption, circuits and systems design.

  • 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS)

    The conference will include regular and special session on emerging electronic systems and design methods, plenary sessions on selected advanced aspects of the theory, design and applications of electronic systems, as well as tutorials given by experts on specific topics.

  • 2011 IEEE 9th International New Circuits and Systems Conference (NEWCAS)

    NEWCAS is a major international conference presenting design methodologies, techniques and experimental results in emerging electronics, circuits and systems topics. The NEWCAS conference deals with analog and digital signal processing, low power consumption, circuits and systems design.

  • 2010 8th IEEE International NEWCAS Conference (NEWCAS)

    The conference will include regular and special session on emerging electronic systems and design methods, plenary sessions on selected advanced aspects of the theory, design and applications of electronic systems, as well as tutorials given by experts on specific topics.

  • 2009 Joint IEEE North-East Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA 2009)

    Advance in microelectronics in addition to signal analog processing, and their applications to telecommunications, artificial vision and biomedical. This include: system architectures, circuit (digital, analog and mixed) and system-level design, test and verification, data and signal processing, microsystems, memories and sensors and associated analog processing, mathematical methods and design tools.

  • 2008 Joint IEEE North-East Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA 2008)

    Advanced research in microelectronics and microsystems constitutes the highlights of the NEWCAS conferences in addition to topics regarding analog data and signal processing and their applications well-established in the TAISA conferences.

  • 2006 IEEE North-East Workshop on Circuits and Systems (NEWCAS 2006)

  • 2005 IEEE North-East Workshop on Circuits and Systems (NEWCAS 2005)

  • 2004 IEEE North-East Workshop on Circuits and Systems (NEWCAS 2004)


2018 19th International Symposium on Quality Electronic Design (ISQED)

19th International Symposium on Quality Electronic Design (ISQED 2018) is the premier interdisciplinary and multidisciplinary Electronic Design conference?bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integratedcircuit technologies, semiconductor technology,packaging, assembly & test to achieve design quality.


2018 31st IEEE International System-on-Chip Conference (SOCC)

System on Chip


2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

The International Symposium on Microarchitecture (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers.

  • 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

    MICRO is the forum for presentation and discussion of new ideas in microarchitectures, compilers, hardware/software interfaces, and design of advanced computing and communication systems.

  • 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

    MICRO is the forum for presentation and discussion of new ideas in microarchitectures, compilers, hardware/software interfaces, and design of advanced computing and communication systems.

  • 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

    Forum for presenting and discussing innovative microarchitecture ideas and techniques foradvanced computing and communication systems, providing a close interaction betweenacademic researchers andindustrial designers and bringing together researchers in fields related to microarchitecture,compilers, chips, andsystems for technical exchange on traditional microarchitecture topics and emerging researchareas.

  • 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

    Forum for presenting and discussing innovative microarchitecture ideas and techniques foradvanced computing and communication systems, providing a close interaction betweenacademic researchers andindustrial designers and bringing together researchers in fields related to microarchitecture,compilers, chips, andsystems for technical exchange on traditional microarchitecture topics and emerging researchareas.

  • 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

    Forum for presenting and discussing innovative microarchitecture ideas and techniques foradvanced computing and communication systems, providing a close interaction between academic researchers andindustrial designers and bringing together researchers in fields related to microarchitecture, compilers, chips, andsystems for technical exchange on traditional microarchitecture topics and emerging research areas.

  • 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

    Forum for presenting and discussing innovative microarchitecture ideas and techniques for advanced computing and communication systems, providing a close interaction between academic researchers and industrial designers and bringing together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas.

  • 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

    The International Symposium on Microarchitecture (MICRO) is the premier forum for presenting, discussing, and debating new and innovative microarchitecture ideas and techniques for advanced computing and communication systems. The goals of this symposium are to bring together researchers in fields related to microarchitecture, compilers, and systems for technical exchange on traditional microarchitectural topics as well as emerging research areas. Historically, the MICRO community has enjoyed having close interaction between academic researchers and industrial designers; we aim to continue and emphasize this tradition at MICRO-44.

  • 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

    MICRO-43 is the premier forum for presenting, discussing and debating new and innovative microarchitecture ideas and techniques for advanced computing and communication systems. The goal of this symposium is to bring together researchers in fields related to processor architecture, compilers, and systems, for technical exchange on traditional MICRO topics as well as new emerging research areas.

  • 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

    MICRO is the premier forum for presenting, discussing and debating new and innovative microarchitecture ideas and techniques for advanced computing and communication systems. The goal of this symposium is to bring together researchers in fields related to processor architecture, compilers, and systems, for technical exchange on traditional MICRO topics as well as new emerging research areas.

  • 2008 41st IEEE/ACM International Symposium on Microarchitecture (MICRO)

    The 41st International Symposium on Microarchitecture is the premier forum for presenting, discussing, and debating new and innovative microarchitecture ideas and techniques for advanced computing and communication systems. This symposium brings together researchers in fields related to microarchitecture, compilers, and systems for technical exchange on traditional microarchitectural topics and emerging research areas.

  • 2007 40th IEEE/ACM International Symposium on Microarchitecture (MICRO)

    MICRO is the premier forum for presenting, discussing and debating new and innovative microarchitecture ideas and techniques for advanced computing and communication systems. The goal of this symposium is to bring together researchers in fields related to processor architecture, compilers, and systems, for technical exchange on traditional MICRO topics as well as new emerging research areas.

  • 2006 39th IEEE/ACM International Symposium on Microarchitecture (MICRO)

  • 2005 38th IEEE/ACM International Symposium on Microarchitecture (MICRO)


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Periodicals related to Network-on-chip

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Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems Magazine, IEEE


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


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Most published Xplore authors for Network-on-chip

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Xplore Articles related to Network-on-chip

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Traffic Allocation: An efficient adaptive network-on-chip routing algorithm design

2016 2nd IEEE International Conference on Computer and Communications (ICCC), 2016

In recent years, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on- chip communication architectures are still facing great challenges. To address the deficiencies of the existing routing ...


Biomimicry to network on chip: Router heart rate

2015 27th International Conference on Microelectronics (ICM), 2015

The growing complexity of systems-on-chip creates the need to replace the bus- based architecture. Network-on-chip has been proposed to address the communication bottleneck of system-on-chip. Router is the key component of network-on-chip architecture. Router frequency is one of the critical parameters, which has direct impact on network-on-chip performance. This paper proposes an adaptive scheme for controlling the router frequency based ...


A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler

2014 IEEE COOL Chips XVII, 2014

A 36 Heterogeneous multicore processor is proposed to accelerate recognition- based markerless augmented reality. To enable a real-time operation of the proposed augmented reality, task-level pipelined multicore architecture with DLP/TLP optimized SIMD processing elements is implemented. In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task- level pipeline. As ...


A strategy for fault tolerant reconfigurable Network-on-Chip design

2016 20th International Symposium on VLSI Design and Test (VDAT), 2016

In this work we have proposed a fault tolerant reconfigurable Network-on-Chip (NoC) architecture that can endure router faults with graceful degradation in network performance. The routers which form the main building block of the interconnect network, have been modified to support multi-core connections. In case of router faults, the modified routers help to recover the healthy cores connected with the ...


A study of CSMA-based and token-based wireless interconnects network-on-chip

2014 IEEE International Conference on Communiction Problem-solving, 2014

The token passing multiple access (TPMA) scheme is a common adopted scheme for wireless network-on-chip (WiNoC) in chip multi-processors (CMPs). The drawback of TPMA is the channel access delay due to TPMA passing the token in a round- robin manner no matter the node has packets to send. In this paper, we study the performance of the slotted p-persistent carrier ...


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Educational Resources on Network-on-chip

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IEEE-USA E-Books

  • Traffic Allocation: An efficient adaptive network-on-chip routing algorithm design

    In recent years, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on- chip communication architectures are still facing great challenges. To address the deficiencies of the existing routing algorithms, a new adaptive network- on-chip routing algorithm: Traffic Allocation routing algorithm is proposed in this paper. The specifics of Traffic Allocation routing as well as the simulation results and analysis are also presented. For the proposed algorithm, traffic allocation registers are added to each of the routers to keep track of communication traffic loads for the four outgoing directions. Instead of monitoring the buffer depth of the neighboring routers, the proposed Traffic Allocation routing measures traffic loads based on local computation so as to reduce extra communication overhead. Simulation of the proposed Traffic Allocation routing algorithm and three existing routing algorithms has been carried out on NIRGAM network-on-chip simulator. Simulation results illustrate that the performance of the Traffic Allocation routing algorithm matches or exceeds the performance of the existing routing algorithms.

  • Biomimicry to network on chip: Router heart rate

    The growing complexity of systems-on-chip creates the need to replace the bus- based architecture. Network-on-chip has been proposed to address the communication bottleneck of system-on-chip. Router is the key component of network-on-chip architecture. Router frequency is one of the critical parameters, which has direct impact on network-on-chip performance. This paper proposes an adaptive scheme for controlling the router frequency based on biomimicry. A complete evaluation for the proposed scheme over various network-on-chip sizes and different evaluation parameters are performed. Results show improvement in throughput and latency. Moreover, it saves up to 75% of buffer storage, up to 60% of dynamic power and achieving load balance for all routers in the network.

  • A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler

    A 36 Heterogeneous multicore processor is proposed to accelerate recognition- based markerless augmented reality. To enable a real-time operation of the proposed augmented reality, task-level pipelined multicore architecture with DLP/TLP optimized SIMD processing elements is implemented. In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task- level pipeline. As a result, it achieves 1.22TOPS peak performance and 1.57TOPS/W energy-efficiency, which are 88% and 76% improvement over a state- of-the-art augmented reality processor, for 30fps 720p test input video.

  • A strategy for fault tolerant reconfigurable Network-on-Chip design

    In this work we have proposed a fault tolerant reconfigurable Network-on-Chip (NoC) architecture that can endure router faults with graceful degradation in network performance. The routers which form the main building block of the interconnect network, have been modified to support multi-core connections. In case of router faults, the modified routers help to recover the healthy cores connected with the faulty routers by dynamically reconfiguring itself and updating the routing table associated with individual routers.

  • A study of CSMA-based and token-based wireless interconnects network-on-chip

    The token passing multiple access (TPMA) scheme is a common adopted scheme for wireless network-on-chip (WiNoC) in chip multi-processors (CMPs). The drawback of TPMA is the channel access delay due to TPMA passing the token in a round- robin manner no matter the node has packets to send. In this paper, we study the performance of the slotted p-persistent carrier sense multiple access (CSMA) scheme on WiNoC. A comprehensive comparison of TPMA and CSMA is given in terms of throughput and access delay in this paper. Based on the study, we show that an appropriate p for the slotted CSMA can be obtained to achieve a high performance WiNoC for CMPs.

  • HM-Mesh: Energy Efficient Hybrid Multiple Network-on-Chip

    With the development of multiple processors SoC (system on chip), there are more and more challenges to the design of NoC (network-on-chip), one of which is to design energy-efficient NoC architecture, due to its large power consumption. Multi-NoC (multiple network-on-chip) has been proposed to save leakage power for its advantages in power gating network components. In this paper, we propose a hybrid Multi-NoC design, called HM-Mesh. HM-Mesh adopts a hybrid CMesh and Mesh architecture, and leverages CMesh network to respect its power efficiency at low network utilization. HMMesh is able to adaptively schedule packets to different subnets according to the network load, and smartly perform power gating to achieve good energy efficiency. The experimental results show that HMMesh delivers an average of 4.87% higher performance than Catnap, the state of the art power efficient Multi-NoC design. More importantly, HM-Mesh consumes an average of 29.2% less power than that of Catnap.

  • Efficient Router Architecture, Design and Performance Exploration for Many-Core Hybrid Photonic Network-on-Chip (2D-PHENIC)

    Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per- watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network- on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.

  • Network-on-Chip Implementation of Midimew-Connected Mesh Network

    Architecture of interconnection network plays a significant role in the performance and energy consumption of Network-on-Chip (NoC) systems. In this paper we propose NoC implementation of Midi mew-connected Mesh Network (MMN). MMN is a Minimal Distance Mesh with Wrap-around (Midi mew) links network of multiple basic modules, in which the basic modules are 2D-mesh networks that are hierarchically interconnected for higher-level networks. For implementing all the links of level-3 MMN, minimum 4 layers are needed which is feasible with current and future VLSI technologies. With innovative combination of diagonal and hierarchical structure, MMN possesses several attractive features including constant node degree, small diameter, low cost, small average distance, and moderate bisection width than that of other conventional and hierarchical interconnection networks.

  • A configurable, programmable and software-defined network on chip

    The rapidly developing multi-cores integration on a chip requires efficient networking. To catch up the evolvement of on-chip network technologies and reduce the cost of redesign and redeployment, the software-defined solution is required on chip instead of proprietary design and straightforward replacement of hardware. In this paper, we propose the software defined on-chip network (SDNoC), which is a configurable and programmable network on chip with the idea of software defined networking. SDNoC separates on-chip network into the control plane and data forwarding plane, so that control logic is decoupled from the underlying chip hardware, and applications are able to configure the network according to their requirements. The simulation evaluates the SDNoC compared with the static and dynamic routing schemes in the traditional on- chip network, and shows SDNoC is able to improve the network performance and reduce power consumption with the programmable control logic and application- specific configuration.

  • ZigZag: An efficient deterministic Network-on-chip routing algorithm design

    As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip communication architectures are still facing great challenges. To address the deficiencies of the existing routing algorithms, a new deterministic network-on-chip routing algorithm: ZigZag routing algorithm is proposed in this paper. The specifics of the algorithm as well as the simulation results and analysis are also presented. For the proposed ZigZag algorithm, the X direction and Y direction distances are compared. The packets are sent in the direction with the greater distance until they become equal at which point, the packets sent alternates between the X direction and the Y direction until they reach their destination. Simulation of the proposed ZigZag routing algorithm and two existing routing algorithms have been carried out on NIRGAM network-on-chip simulator. Simulation results illustrate that the performance of the ZigZag routing algorithm matches or exceeds the performance of the existing routing algorithms.



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