Conferences related to Network-on-chip

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2015 IEEE International Reliability Physics Symposium (IRPS)

Sharing information related to cause, effects and solutions in the deign and manufacture of electronics and related components


2013 IEEE International 3D Systems Integration Conference (3DIC)

Technologies for enabling 3D systems based on Through Silicon Vias.

  • 2011 IEEE International 3D Systems Integration Conference (3DIC)

    3DIC 2012 will cover all 3D Integration topics, including 3D process technology, materials, equipment, circuits technology, design and test methodology and applications. The conference invites authors and attendees to submit and interact with 3D integration researchers from all around the world.

  • 2010 IEEE International 3D Systems Integration Conference (3DIC)

    3DIC 2010 will cover all 3D Integration topics, including 3D process technology, materials, equipment, circuits technology, design methodology and applications.

  • 2009 3rd International Conference on 3D System Integration (3DIC)

    covers all the topics in 3DIC, including 3D process technology, materials, equipment, circuits technology, design methodology and applications.


2013 IEEE International Integrated Reliability Workshop (IIRW)

We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits,systems, processes), customer product reliability requirements / manufacturer reliability tasks, waferlevel reliability tests (test approaches and reliability test structures), reliability modeling and simulation,optoelectronics, and single event upsets.

  • 2012 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.

  • 2011 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems through tutorials, paper presentations, discussion groups and special interest groups.

  • 2010 IEEE International Integrated Reliability Workshop (IIRW)

    The Integrated Reliability Workshop focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and f

  • 2009 IEEE International Integrated Reliability Workshop (IRW)

    Semiconductor Reliability in general; and Wafer Level Reliability in specific. Covering areas like (but not limited to): Design-in Reliability, reliability characterization, deep sub-micron transistor and circuit reliability, customer reliability requirements, wafer level reliability tests, and reliability root cause analysis, etc.

  • 2008 IEEE International Integrated Reliability Workshop (IRW)

    The workshop focuses on ensuring device reliability through fabrication, design, testing, characterization and simulation as well as identification of the defects and mechanisms responsible for reliability problems. It provides a unique environment for understanding, developing and sharing reliability technology and test methodology.

  • 2007 IEEE International Integrated Reliability Workshop (IRW)

    The Workshop focuses on ensuring semiconductor reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliabilty problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding and developing reliability technology and test methodology.

  • 2006 IEEE International Integrated Reliability Workshop (IRW)


2013 International Conference on Anti-Counterfeiting, Security and Identification (ASID)

Micro/Nano-sensor and BioMEMSIC Design and System IntegrationMulti-core Processor and Reconfigurable ComputingCloud Computing & Internet of Things (IoT)Cryptographic Algorithm and Security ManagementNext Generation Networking and IPv6Wireless Communication and Networking EngineeringCognitive Radio and Software Defined RadioEMC Theory and RFID TechniquesPattern Recognition and Applications

  • 2012 International Conference on Anti-Counterfeiting, Security and Identification (2012 ASID)

    Cloud Computing, RFID Techniques and applications, IC Design and System Integration, Pattern recognition and applications, Cryptographic algorithm and security Management, Cognitive Radio and Software Defined Radio, Next Generation Networking and IPv6, Wireless communication and Networking engineering, EMC Theory and applications, Internet of Things (IoT).

  • 2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification (2011 ASID)

    Internet of Things (IoT) RFID Techniques and applications IC Design and System Integration EMC Theory and applications Pattern recognition and applications Cryptograph standards and management Wireless communication and Networking engineering Next Generation Networking and IPv6 Information Management and polices Conference Keywords: anti-counterfeiting, security, identification, asid, rfid, and antenna, network security,internet of things, rfid techniques and applications, wireless com

  • 2010 International Conference on Anti-Counterfeiting, Security and Identification (2010 ASID)

    Live demonstrations describing novel work on systems, applications and services of the Internet reaching out into the real world of physical objects, problems related to RFID and Antenna, IC Design and System Integration, Wireless Communication and Network Security, Cryptographic Algorithm and Hardware Implementation, Anti-counterfeiting and Identification, Information Management and Industries Polices.

  • 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication (2009 ASID)

    RFID and Antenna, Wireless Comm and Network Security, Cryptographical Algorithm and realization on hardward, Anti-counterfeiting and Identification, Information management and industries polices


TENCON 2013 - 2013 IEEE Region 10 Conference

Communication and network,Signal and information processing,Automatic control,Computational intelligence,Intelligent transportation,Grid and cloud computing,Cognitive radio and system,Internet of things,Computer science and technology,Audio and speech processing,Electronic devices,Circuits and systems,Power and energy,Microwave, antennas and propagation,Information and data security,System design and implementation

  • TENCON 2012 - 2012 IEEE Region 10 Conference

    TENCON is a general engineering conference covering electrical and electronics engineering and computer science. The theme of the conference is "Sustainable Development through Humanitarian Technology". The conference will be organized under several different tracks consisting of power engineering, signal processing, communications, computing, circuits and systems, software systems and the theme.

  • TENCON 2011 - 2011 IEEE Region 10 Conference

    Trends and Development in Converging Technology towards 2020

  • TENCON 2010 - 2010 IEEE Region 10 Conference

    Information and Communication Technologies

  • TENCON 2009 - 2009 IEEE Region 10 Conference

    The theme of the conference is "Emerging Technologies for Sustainable Development". Topics of interest include, but are not limited to, Power and Energy; Signal Processing; Networks and Communications; Circuits and Systems; Computational Intelligence; Computing Architectures & Systems; Software and Database Systems.

  • TENCON 2008 - 2008 IEEE Region 10 Conference

    TENCON 2008 is a general engineering conference covering electrical and electronics engineering and computer science. The theme of the conference is 'innovative technologies for societal transformation'. The conference will be organized under seven different tracks consisting of power engineering, signal processing, communications, computing, circuits and systems, software systems and the theme.


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Periodicals related to Network-on-chip

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Circuits and Systems Magazine, IEEE


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...




Xplore Articles related to Network-on-chip

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A General Fault-Tolerant Minimal Routing for Mesh Architectures

Hongzhi Zhao; Nader Bagherzadeh; Jie Wu IEEE Transactions on Computers, 2017

Fault-tolerant minimal routing algorithms aim at finding a Manhattan path between the source and destination nodes and route around all faulty nodes. Additionally, some non-faulty nodes that are helpless to make up of a fault- tolerant minimal path should also be routed around. How to label such non- faulty nodes efficiently is a major challenge. State-of-the-art solutions could not address ...


Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration

Leandro Soares Indrusiak; Osmar Marchi dos Santos 2011 Design, Automation & Test in Europe, 2011

Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on- chip interconnects through transaction-level modelling (TLM). A particular on- chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a ...


Self-sustained activity in attractor networks using neuromorphic VLSI

Patrick Camilleri; Massimiliano Giulioni; Maurizio Mattia; Jochen Braun; Paolo Del Giudice The 2010 International Joint Conference on Neural Networks (IJCNN), 2010

We describe and demonstrate the implementation of attractor neural network dynamics in analog VLSI chips. The on-chip network is composed of an excitatory and an inhibitory population of recurrently connected linear integrate-and-fire neurons. Besides the recurrent input these two populations receive external input in the form of spike trains from an Address-Event- Representation (AER) based system. External AER input stimulates ...


Soft-error resilient Network-on-Chip for safety-critical applications

Khanh N. Dang; Yuichi Okuyama; Abderazek Ben Abdallah 2016 International Conference on IC Design and Technology (ICICDT), 2016

Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the packet switched NoC paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors have severe consequences on system performance, such as deadlock, data ...


Network-on-Chip aware scheduling of hard-real-time tasks

Mayank Shekhar; Harini Ramaprasad; Frank Mueller Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems (SIES 2014), 2014

As real-time systems continue to integrate more and more functionality, powerful multi-core architectures are the only viable solution to meet their computational demands under reasonable energy budgets. Dramatic increases in the number of cores on multi-core architectures have led to scalability issues. Modern platforms are moving away from designs with shared caches and shared buses to designs with private caches ...


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Educational Resources on Network-on-chip

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eLearning

A General Fault-Tolerant Minimal Routing for Mesh Architectures

Hongzhi Zhao; Nader Bagherzadeh; Jie Wu IEEE Transactions on Computers, 2017

Fault-tolerant minimal routing algorithms aim at finding a Manhattan path between the source and destination nodes and route around all faulty nodes. Additionally, some non-faulty nodes that are helpless to make up of a fault- tolerant minimal path should also be routed around. How to label such non- faulty nodes efficiently is a major challenge. State-of-the-art solutions could not address ...


Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration

Leandro Soares Indrusiak; Osmar Marchi dos Santos 2011 Design, Automation & Test in Europe, 2011

Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on- chip interconnects through transaction-level modelling (TLM). A particular on- chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a ...


Self-sustained activity in attractor networks using neuromorphic VLSI

Patrick Camilleri; Massimiliano Giulioni; Maurizio Mattia; Jochen Braun; Paolo Del Giudice The 2010 International Joint Conference on Neural Networks (IJCNN), 2010

We describe and demonstrate the implementation of attractor neural network dynamics in analog VLSI chips. The on-chip network is composed of an excitatory and an inhibitory population of recurrently connected linear integrate-and-fire neurons. Besides the recurrent input these two populations receive external input in the form of spike trains from an Address-Event- Representation (AER) based system. External AER input stimulates ...


Soft-error resilient Network-on-Chip for safety-critical applications

Khanh N. Dang; Yuichi Okuyama; Abderazek Ben Abdallah 2016 International Conference on IC Design and Technology (ICICDT), 2016

Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the packet switched NoC paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors have severe consequences on system performance, such as deadlock, data ...


Network-on-Chip aware scheduling of hard-real-time tasks

Mayank Shekhar; Harini Ramaprasad; Frank Mueller Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems (SIES 2014), 2014

As real-time systems continue to integrate more and more functionality, powerful multi-core architectures are the only viable solution to meet their computational demands under reasonable energy budgets. Dramatic increases in the number of cores on multi-core architectures have led to scalability issues. Modern platforms are moving away from designs with shared caches and shared buses to designs with private caches ...


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IEEE.tv Videos

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IEEE-USA E-Books

  • Application Platform

    This chapter contains sections titled: SoC Design Paradigms System Architecture Low-power SoC Design Network-on-Chip based SoC References

  • Time-Average-Frequency and Special Clocking Techniques: Gapped Clock, Stretchable Clock, and Pausible Clock

    Gapped clocking is a commonly used technique in optical transport networks (OTNs), broadcast video, and other applications. This chapter discusses the stretchable and pausible clock in connection with the application environment of a NoC (network-on-chip). The gapped clock is produced by removing pulses from a clock signal generated by an untouchable clock source. The chapter also discusses the techniques, including the gapped clock, stretchable clock, pausible clock, and possible others all have the Time-Average-Frequency (TAF) concept work behind the scene. All these special clocking techniques illustrate the fact that the essence of clock frequency is the accomplishment of a specified number of operations within the time window of 1 s. An important topic related to the gapped clock, pausible clock, and stretched clock is clock jitter. It is crucial to understand that the pulse-length modification introduced by these special clocking techniques is an intended operation.



Standards related to Network-on-chip

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