Conferences related to Digital Circuits

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2018 IEEE Symposium on VLSI Circuits

Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2020 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2016 IEEE Symposium on VLSI Circuits

    circuit design to address challenges of deeply scaled technologies - e.g. dfm, variability, reliability - digital circuit techniques - analog and mixed signal circuits such as data converters and amp

  • 2014 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2012 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation

  • 2011 Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2010 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2009 Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies

  • 2008 IEEE Symposium on VLSI Circuits

  • 2007 IEEE Symposium on VLSI Circuits


2018 IEEE Symposium on VLSI Technology

New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2020 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2016 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2014 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2012 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2011 Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2010 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2009 IEEE Symposium on VLSI Technology

    - New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D-system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices

  • 2008 IEEE Symposium on VLSI Technology

  • 2007 IEEE Symposium on VLSI Technology

  • 2006 IEEE Symposium on VLSI Technology


2017 IEEE International Solid- State Circuits Conference - (ISSCC)

The International Solid-State Circuits Conference is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS IC's.


2014 IEEE Custom Integrated Circuits Conference - CICC 2014

The IEEE Custom Integrated Circuits Conference (CICC) is the premier conference devoted to IC development. CICC showcases original, first-published innovative analog and digital circuit techniques covering a broad spectrum of technical topics. It is a forum for circuit, IC and SoC designers, CAD developers, manufacturers and ASIC users. CICC is the conference to find out how to solve design problems and improve circuit design and chip design techniques.


2014 IEEE International Symposium on Circuits and Systems (ISCAS)

The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems Society and the world’s premier networking forum in the highly active fields of theory, design and implementation of circuits and systems.ISCAS 2014 will have a special focus on nano/bio circuits and systems applied to enhancing living and lifestyles, and seeks to address multidisciplinary challenges in healthcare and well-being, the environment and climate change.

  • 2013 IEEE International Symposium on Circuits and Systems (ISCAS)

    The Symposium will focus on circuits and systems employing nanodevices (both extremely scaled CMOS and non-CMOS devices) and circuit fabrics (mixture of standard CMOS and evolving nano-structure elements) and their implementation cost, switching speed, energy efficiency, and reliability. The ISCAS 2010 will include oral and poster sessions; tutorials given by experts in state-of-the-art topics; and special sessions, with the aim of complementing the regular program with topics of particular interest to the community that cut across and beyond disciplines traditionally represented at ISCAS.

  • 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012

    2012 International Symposium on Circuits and Systems (ISCAS 2012) aims at providing the world's premier forum of leading researchers in circuits and systems areas from academia and industries, especially focusing on Convergence of BINET (BioInfoNanoEnviro Tech.) which represents IT, NT and ET and leading Human Life Revolutions. Prospective authors are invited to submit papers of their original works emphasizing contributions beyond the present state of the art. We also welcome proposals on special tuto

  • 2011 IEEE International Symposium on Circuits and Systems (ISCAS)

    The IEEE International Symposium on Circuits and Systems (ISCAS) is the world's premier networking forum of leading researchers in the highly active fields of theory, design and implementation of circuits and systems.

  • 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010

    ISCAS is a unique conference dealing with circuits and systems. It's the yearly "rendez-vous" of leading researchers, coming both from academia and industry, in the highly active fields of theory, design and implementation of circuits and systems. The Symposium will focus on circuits and systems for high quality life and consumer technologies, including mobile communications, advanced multimedia systems, sensor networks and Nano-Bio Circuit Fabrics and Systems.

  • 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009

    Analog Signal Processing, Biomedical Circuits and Systems, Blind Signal Processing, Cellular Neural Networks and Array Computing, Circuits and Systems for Communications, Computer-Aided Network Design, Digital Signal Processing, Life-Science Systems and Applications, Multimedia Systems and Applications, Nanoelectronics and Gigascale Systems, Neural Systems and Applications, Nonlinear Circuits and Applications, Power Systems and Power Electronic Circuits, Sensory Systems, Visual Signal Processing and Communi

  • 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008

  • 2007 IEEE International Symposium on Circuits and Systems - ISCAS 2007

  • 2006 IEEE International Symposium on Circuits and Systems - ISCAS 2006

  • 2005 IEEE International Symposium on Circuits and Systems - ISCAS 2005


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Periodicals related to Digital Circuits

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Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems Magazine, IEEE


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


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Most published Xplore authors for Digital Circuits

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Xplore Articles related to Digital Circuits

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Using level restoring method for dual supply voltage

K. Sadeghi; M. Emadi; F. Farbiz 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006

A new level converter for use in dual voltage SOI digital circuits is presented. This technique uses the idea of keeper transistors, and consumes less power compared to the traditional methods. The effects of load capacitance on the circuit are studied by extensive simulations.


A small test generator for large designs

S. Kundu; L. M. Huisman; I. Nair; V. Ivenaar; L. N. Reddy Proceedings International Test Conference 1992, 1992

We report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. the fraction of faults that are resolved, are comparable to or better than those reported previously in the literature. No preprocessing is required and the amount of memory needed is less than 100 ...


Si Circuits Design Automation Using Ample Language

P. Sniatala; R. Rudnicki Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., 2006

This paper presents AMPLE language utilization for a layout generation. A current mirror generator is described. Next, the proposed solution is presented as a part of a design flow for SI circuits. Another tool improving the design - Current Mirror Maker is also presented. This tool calculates transistors' sizes, which fulfil the given requirements of the circuit for the desired ...


Testing of embedded A/D converters in mixed-signal circuit

N. Ben-Hamida; B. Ayari; B. Kaminska Proceedings International Conference on Computer Design. VLSI in Computers and Processors, 1996

In this paper, a complete functional testing of embedded ADC is presented. The integral non-linearity error, INLE, differential non-linearity error, DNLE, offset error, OSE, gain error and the signal-to-noise ratio, SNR are rested. The problem related to the propagation of the analog signal to the input of the ADC and the observation of the digital output of the converter at ...


Optimization of resistively hardened latches

G. Gagne; Y. Savaria IEEE Transactions on Nuclear Science, 1990

The design of digital circuits tolerant to single-event upsets is considered. The results of a study in which an analytical model was used to predict the behavior of a standard resistively hardened latch are presented. It is shown that a worst-case analysis for all possible single-event upset situations (on the latch or in the logic) can be derived from studying ...


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Educational Resources on Digital Circuits

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eLearning

Using level restoring method for dual supply voltage

K. Sadeghi; M. Emadi; F. Farbiz 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006

A new level converter for use in dual voltage SOI digital circuits is presented. This technique uses the idea of keeper transistors, and consumes less power compared to the traditional methods. The effects of load capacitance on the circuit are studied by extensive simulations.


A small test generator for large designs

S. Kundu; L. M. Huisman; I. Nair; V. Ivenaar; L. N. Reddy Proceedings International Test Conference 1992, 1992

We report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. the fraction of faults that are resolved, are comparable to or better than those reported previously in the literature. No preprocessing is required and the amount of memory needed is less than 100 ...


Si Circuits Design Automation Using Ample Language

P. Sniatala; R. Rudnicki Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006., 2006

This paper presents AMPLE language utilization for a layout generation. A current mirror generator is described. Next, the proposed solution is presented as a part of a design flow for SI circuits. Another tool improving the design - Current Mirror Maker is also presented. This tool calculates transistors' sizes, which fulfil the given requirements of the circuit for the desired ...


Testing of embedded A/D converters in mixed-signal circuit

N. Ben-Hamida; B. Ayari; B. Kaminska Proceedings International Conference on Computer Design. VLSI in Computers and Processors, 1996

In this paper, a complete functional testing of embedded ADC is presented. The integral non-linearity error, INLE, differential non-linearity error, DNLE, offset error, OSE, gain error and the signal-to-noise ratio, SNR are rested. The problem related to the propagation of the analog signal to the input of the ADC and the observation of the digital output of the converter at ...


Optimization of resistively hardened latches

G. Gagne; Y. Savaria IEEE Transactions on Nuclear Science, 1990

The design of digital circuits tolerant to single-event upsets is considered. The results of a study in which an analytical model was used to predict the behavior of a standard resistively hardened latch are presented. It is shown that a worst-case analysis for all possible single-event upset situations (on the latch or in the logic) can be derived from studying ...


More eLearning Resources

IEEE.tv Videos

Analog to Digital Types
The Josephson Effect: Josephson Digital Electronics in the Soviet Union
2017 IEEE Donald O. Pederson Award in Solid-State Circuits: Takao Nishitani and John S. Thompson
Interview with Takao Nishitani - IEEE Donald O. Pederson Award in Solid-State Circuits Co-Recipient 2017
Co-design of Power Amplifier and Dynamic Power Supplies for Radar and Communications Transmitters
ASC-2014 SQUIDs 50th Anniversary: 1 of 6 Arnold Silver
Analog to Digital Traits
Superconductive Energy-Efficient Computing - ASC-2014 Plenary-series - 6 of 13 - Wednesday 2014/8/13
IMS 2011-100 Years of Superconductivity (1911-2011) - Existing and Emerging RF Applications of Superconductivity
Analog Devices, Inc. accepts the IEEE Corporate Innovation Award - Honors Ceremony 2017
Low-energy High-performance Computing based on Superconducting Technology
IEEE Custom Integrated Circuits Conference
Voltage Metrology with Superconductive Electronics
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
R. Jacob Baker: CMOS & DRAM Circuit Design
Coherent Photonic Architectures: The Missing Link? - Hideo Mabuchi: 2016 International Conference on Rebooting Computing
IEEE PELS Webinar Series-Galvanic Isolation for Power Supply Applications
Brooklyn 5G Summit: Going the Distance with CMOs: mm-Waves and Beyond
ISSCC 2012 - Awards Ceremony
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation

IEEE-USA E-Books

  • No title

    The Boolean Differential Calculus (BDC) is a very powerful theory that extends the structure of a Boolean Algebra significantly. Based on a small number of definitions, many theorems have been proven. The available operations have been efficiently implemented in several software packages. There is a very wide field of applications. While a Boolean Algebra is focused on values of logic functions, the BDC allows the evaluation of changes of function values. Such changes can be explored for pairs of function values as well as for whole subspaces. Due to the same basic data structures, the BDC can be applied to any task described by logic functions and equations together with the Boolean Algebra. The BDC can be widely used for the analysis, synthesis, and testing of digital circuits. Generally speaking, a Boolean differential equation (BDE) is an equation in which elements of the BDC appear. It includes variables, functions, and derivative operations of these functions. The solution of su h a BDE is a set of Boolean functions. This is a significant extension of Boolean equations, which have sets of Boolean vectors as solutions. In the simplest BDE a derivative operation of the BDC on the left-hand side is equal to a logic function on the right-hand side. The solution of such a simple BDE means to execute an operation which is inverse to the given derivative. BDEs can be applied in the same fields as the BDC, however, their possibility to express sets of Boolean functions extends the application field significantly.

  • About the Author

    This book explains, in lay terms, the surprisingly simple system of mathematical logic used in digital computer circuitry. Anecdotal in its style and often funny, it follows the development of this logic system from its origins in Victorian England to its rediscovery in this century as the foundation of all modern computing machinery. ONES AND ZEROS will be enjoyed by anyone who has a general interest in science and technology.

  • Appendix C: Summary of Boolean Functions

    This book explains, in lay terms, the surprisingly simple system of mathematical logic used in digital computer circuitry. Anecdotal in its style and often funny, it follows the development of this logic system from its origins in Victorian England to its rediscovery in this century as the foundation of all modern computing machinery. ONES AND ZEROS will be enjoyed by anyone who has a general interest in science and technology.

  • Experimental Results and Modeling Techniques for Substrate Noise in MixedSignal Integrated Circuits

    Switching transients in digital MOS circuits can perturb analog circuits integrated on the same die by means of coupling through the substrate. This paper describes an experimental technique for observing the effects of such substrate noise. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low- inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprised of an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is more effective than either physical separation or guard rings in minimizing substrate crosstalk between analog and digital circuits fabricated on epitaxial substrates. To enhance understanding of the experimental results, two-dimensional device simulations are used to show how crosstalk propagates via the heavily doped bulk. Device simulations are also used to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. Finally, a method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates has been developed using a single-node substrate model.

  • Metrics, Techniques and Recent Developments in MixedSignal Testing

    This paper presents a tutorial on mixed-signal testing. Our focus is on testing the analog portion of the mixed-signal device, as the digital portion is handled in the usual way. We begin by first outlining the role of test in a manufacturing environment, and its impact on product cost and quality. We will look at the impact of manufacturing defects on the behavior of digital and analog circuits. Subsequently, we will argue that analog circuits require very different test methods than those presently used to test digital circuits. We will then describe four common analog test methods and their measurement setups. We will also describe how analog testing can be accomplished using digital sampling techniques. Finally, we shall close this tutorial with a brief description of several developments presently underway on the design of testable mixed-signal circuits

  • Low Power Digital Design

    This part contains sections titled: Introduction Sources of power dissipation in digital circuits Low power CMOS design A case study Summary This part contains sections titled: References

  • No title

    Modeling Digital Switching Circuits with Linear Algebra describes an approach for modeling digital information and circuitry that is an alternative to Boolean algebra. While the Boolean algebraic model has been wildly successful and is responsible for many advances in modern information technology, the approach described in this book offers new insight and different ways of solving problems. Modeling the bit as a vector instead of a scalar value in the set {0, 1} allows digital circuits to be characterized with transfer functions in the form of a linear transformation matrix. The use of transfer functions is ubiquitous in many areas of engineering and their rich background in linear systems theory and signal processing is easily applied to digital switching circuits with this model. The common tasks of circuit simulation and justification are specific examples of the application of the linear algebraic model and are described in detail. The advantages offered by the new model as compa ed to traditional methods are emphasized throughout the book. Furthermore, the new approach is easily generalized to other types of information processing circuits such as those based upon multiple-valued or quantum logic; thus providing a unifying mathematical framework common to each of these areas. Modeling Digital Switching Circuits with Linear Algebra provides a blend of theoretical concepts and practical issues involved in implementing the method for circuit design tasks. Data structures are described and are shown to not require any more resources for representing the underlying matrices and vectors than those currently used in modern electronic design automation (EDA) tools based on the Boolean model. Algorithms are described that perform simulation, justification, and other common EDA tasks in an efficient manner that are competitive with conventional design tools. The linear algebraic model can be used to implement common EDA tasks directly upon a structural netlist thus avo ding the intermediate step of transforming a circuit description into a representation of a set of switching functions as is commonly the case when conventional Boolean techniques are used. Implementation results are provided that empirically demonstrate the practicality of the linear algebraic model.

  • Further Reading

    The prelims comprise: Digital Electronics and Engineering Abstract Mathematics and Algebras History of Symbolic Logic and Boolean Algebra Mathematical Logic Number Systems and General Mathematics History of Computers Syllogistic Reasoning

  • About the Editor

    "This comprehensive collection of papers offers you practical information that can be used to develop high-performance digital system design. Specially written introductions by editor Vojin G. Oklobdzija precede each chapter to aid your understanding of the most relevant topics in this advanced area of circuit design. Featured topics include: * Differential pass-transistor logic * High-speed circuits and design of high-performance systems * Advanced deep submicron circuits used in high-speed computers and digital circuits * Clocking and latch design essential to high-performance systems * Relationships between VLSI algorithms and implementation techniques HIGH PERFORMANCE SYSTEM DESIGN: Circuits and Logic is indispensable reading for circuit designers, practicing engineers, and students who want to master the basic principles underlying high-performance system design. This handy, single volume provides a useful reference to a collection of accumulated experience necessary for good, successful designs. Professors: To request an examination copy simply e-mail collegeadoption@ieee.org." Sponsored by: IEEE Solid-State Circuits Council/Society.

  • Combinational Circuits

    This chapter contains sections titled: Introduction to Digital Circuits Binary Numbers: a Quick Introduction Boolean Algebra Minterms: Standard or Canonical Sum of Products (SOP) Form Maxterms: Standard or Canonical Product of Sums (POS) Form Karnaugh Maps and Design Examples Product of Sums Simplifications Don't Care Conditions Logic Gates: Electrical and Timing Characteristics Summary Further Reading Problems



Standards related to Digital Circuits

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No standards are currently tagged "Digital Circuits"