Conferences related to Digital Circuits

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2018 15th International Workshop on Advanced Motion Control (AMC)

1. Advanced Motion Control2. Haptics, Robotics and Human-Machine Systems3. Micro/Nano Motion Control Systems4. Intelligent Motion Control Systems5. Nonlinear, Adaptive and Robust Control Systems6. Motion Systems for Robot Intelligence and Humanoid Robotics7. CPG based Feedback Control, Morphological Control8. Actuators and Sensors in Motion System9. Motion Control of Aerial/Ground/Underwater Robots10. Advanced Dynamics and Motion Control11. Motion Control for Assistive and Rehabilitative Robots and Systems12. Intelligent and Advanced Traffic Controls13. Computer Vision in Motion Control14. Network and Communication Technologies in Motion Control15. Motion Control of Soft Robots16. Automation Technologies in Primary Industries17. Other Topics and Applications Involving Motion Dynamics and Control


2018 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES)

The conference will deal will all aspects of power electronics, motor drives and Power electronics applications to energy systems.


2018 IEEE Symposium on VLSI Circuits

Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2020 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2016 IEEE Symposium on VLSI Circuits

    circuit design to address challenges of deeply scaled technologies - e.g. dfm, variability, reliability - digital circuit techniques - analog and mixed signal circuits such as data converters and amp

  • 2014 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2012 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation

  • 2011 Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2010 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2009 Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies

  • 2008 IEEE Symposium on VLSI Circuits

  • 2007 IEEE Symposium on VLSI Circuits


2018 IEEE Symposium on VLSI Technology

New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2020 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2016 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2014 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices.

  • 2012 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2011 Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2010 IEEE Symposium on VLSI Technology

    New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D - system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices -

  • 2009 IEEE Symposium on VLSI Technology

    - New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) - Advanced gate stack and interconnect in VLSI processes and devices - Advanced lithography and fine patternig technologies for high density VLSI - New functional devices beyond CMOS with a path for VLSI implantation - Packing of VLSI devices including 3D-system integration - Processes and devices modeling of VLSI devices - Reliability related to the above devices

  • 2008 IEEE Symposium on VLSI Technology

  • 2007 IEEE Symposium on VLSI Technology

  • 2006 IEEE Symposium on VLSI Technology


2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

SMACD is a dedicated forum devoted to Design Methods and Tools for Analog, Mixed-signal, RF (AMS/RF) and multi-domain (MEMs, nanoelectronic, optoelectronic, biological, etc.) integrated circuits and systems.


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Periodicals related to Digital Circuits

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Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems Magazine, IEEE


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Most published Xplore authors for Digital Circuits

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Xplore Articles related to Digital Circuits

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Stability issues in digital circuits in amorphous silicon technology

N. Mohan; K. S. Karim; S. Prakash; A. Nathan Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555), 2001

Hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) are attractive for flat-panel liquid crystal displays (LCDs) and imaging sensor arrays in view of their large area capability. In large area imaging arrays or displays, the need for multiplexer circuits arises because of the large number of external gate and data line connections. This work presents a multiplexer (MUX) design using ...


Physical modeling of beneficial dynamic floating-body effects in non-fully depleted SOI CMOS circuits

Dongwook Suh; J. G. Fossum Proceedings. IEEE International SOI Conference, 1994

The floating-body configuration is desirable in scaled SOI CMOS technology because of area efficacy. Unfortunately it portends various problems, one of which is the premature parasitic-BJT breakdown that occurs in both fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs. In the NFD device, other floating-body effects, some of which can be beneficial, are apparent at drain-source voltages below the ...


Optimization techniques for maximum power-efficiency of deep sub-micron CMOS digital circuits

D. S. C. Kwok; M. Margala 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000

This paper presents results of a study to locate the optimal operating power supply voltage for a maximum power-efficiency operation of CMOS digital circuits in a deep sub-micron environment. The results show that the optimal VDD is a strong function of NMOS and PMOS device threshold voltages and their sizes. Depending on the capacitive loading, the optimal VDD=ξ(|Vtp|+V tn), where ...


Logic analyser systems-today's mixed domain measurement solution

M. D. Chaplain IEE Colloquium on Design and Test of Mixed Analogue and Digital Circuits, 1990

This evolution of the Oscilloscope readily lends itself to modulation and inclusion as part of a Logic Analysis system, thereby adding a third dimension to the instrument, enabling the simultaneous acquisition of relational (state), functional (timing) and parameteric (analogue) data. These three modes of analysis provide the required flexibility to analyse `mixed' devices and circuits. Incorporating the three types of ...


Digital Compensator design for power-aware DC-DC converters

Chun-Nan Liu; Chun-Hung Yang; Chien-Hung Tsai 2010 2nd International Symposium on Aware Computing, 2010

This paper presents a methodology to design a PID Digital Compensator for digital controller power electronics systems. This method is base on direct digital design and use on digital controller buck dc-dc converter. Crossover frequency and phase margin of close-loop system can be set by this method, and the integration coefficient in digital compensator set by this method can be ...


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Educational Resources on Digital Circuits

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eLearning

Stability issues in digital circuits in amorphous silicon technology

N. Mohan; K. S. Karim; S. Prakash; A. Nathan Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555), 2001

Hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) are attractive for flat-panel liquid crystal displays (LCDs) and imaging sensor arrays in view of their large area capability. In large area imaging arrays or displays, the need for multiplexer circuits arises because of the large number of external gate and data line connections. This work presents a multiplexer (MUX) design using ...


Physical modeling of beneficial dynamic floating-body effects in non-fully depleted SOI CMOS circuits

Dongwook Suh; J. G. Fossum Proceedings. IEEE International SOI Conference, 1994

The floating-body configuration is desirable in scaled SOI CMOS technology because of area efficacy. Unfortunately it portends various problems, one of which is the premature parasitic-BJT breakdown that occurs in both fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs. In the NFD device, other floating-body effects, some of which can be beneficial, are apparent at drain-source voltages below the ...


Optimization techniques for maximum power-efficiency of deep sub-micron CMOS digital circuits

D. S. C. Kwok; M. Margala 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000

This paper presents results of a study to locate the optimal operating power supply voltage for a maximum power-efficiency operation of CMOS digital circuits in a deep sub-micron environment. The results show that the optimal VDD is a strong function of NMOS and PMOS device threshold voltages and their sizes. Depending on the capacitive loading, the optimal VDD=ξ(|Vtp|+V tn), where ...


Logic analyser systems-today's mixed domain measurement solution

M. D. Chaplain IEE Colloquium on Design and Test of Mixed Analogue and Digital Circuits, 1990

This evolution of the Oscilloscope readily lends itself to modulation and inclusion as part of a Logic Analysis system, thereby adding a third dimension to the instrument, enabling the simultaneous acquisition of relational (state), functional (timing) and parameteric (analogue) data. These three modes of analysis provide the required flexibility to analyse `mixed' devices and circuits. Incorporating the three types of ...


Digital Compensator design for power-aware DC-DC converters

Chun-Nan Liu; Chun-Hung Yang; Chien-Hung Tsai 2010 2nd International Symposium on Aware Computing, 2010

This paper presents a methodology to design a PID Digital Compensator for digital controller power electronics systems. This method is base on direct digital design and use on digital controller buck dc-dc converter. Crossover frequency and phase margin of close-loop system can be set by this method, and the integration coefficient in digital compensator set by this method can be ...


More eLearning Resources

IEEE-USA E-Books

  • Power Analysis Techniques

    This chapter contains sections titled: Transition Density: A New Measure of Activity in Digital Circuits Estimation of Average Switching Activity in Combinational and Sequential Circuits Power Estimation Methods for Sequential Logic Circuits A Monte Carlo Approach for Power Estimation Stratified Random Sampling for Power Estimation A Survey of High-Level Power Estimation Techniques Activity-Sensitive Architectural Power Analysis Power Analysis of Embedded Software: A First Step Towards Software Power Minimization

  • Chapter 6

    This chapter contains sections titled: Applications of Finite-Difference Time-Domain Technique to Planar Microwave Circuit Design Analysis of an Arbitrarily-Shaped Planar Circuit - A Time-Domain Approach Analysis of Arbitrarily Shaped Two-Dimensional Microwave Circuits by Finite- Difference Time-Domain Method Calculations of the Dispersive Characteristics of Microstrips by the Time- Domain Finite Difference Method Time-Domain Finite Difference Approach to the Calculation of the Frequency- Dependent Characteristics of Microstrip Discontinuities Analysis of Microstrip Circuits Using Three-Dimensional Full-Wave Electromagnetic Field Analysis in the Time Domain Characterization of a 90° Microstrip Bend with Arbitrary Miter via the Time- Domain Finite Difference Method Application of the Three-Dimensional Finite-Difference Time-Domain Method to the Analysis of Planar Microstrip Circuits Full-Wave Analysis of Coplanar Discontinuities Considering Three-Dimensional Bond Wires Analysis of Cross-Talk on High-Speed Digital Circuits Using the Finite Difference Time-Domain Method An Efficient Two-Dimensional Graded Mesh Finite-Difference Time-Domain Algorithm for Shielded or Open Waveguide Structures Steady-State Analysis of Nonlinear Forced and Autonomous Microwave Circuits Using the Compression Approach Computer-Aided Engineering for Microwave and Millimeter-Wave Circuits Using the FD-TD Technique of Field Simulations (Invited Article) FDTD Simulation for Microwave Packages and Interconnects

  • SubstrateAware MixedSignal Macrocell Placement in WRIGHT

    We describe a set of placement algorithms for handling substrate-coupled switching noise. A typical mixed-signal IC has both sensitive analog and noisy digital circuits, and the common substrate parasitically couples digital switching transients into the sensitive analog regions of the chip. To preserve the integrity of sensitive analog signals, it is thus necessary to electrically isolate the analog and digital. We argue that optimal area utilization requires such isolation be designed into the system during first- cut chip-level placement. We present algorithms that incorporate commonly used isolation techniques within an automatic placement framework. Our substrate- noise evaluation mechanism uses a simplified substrate model and simple electrical representations for the noisy digital macrocells. The digital/analog interactions determined through these models are incorporated into a simulated annealing macrocell placement framework. Automatic placement results indicate these substrateaware algorithms allow efficient mixed-signal placement optimization.

  • Frontmatter

    The prelims comprise: Half Title Book Series Title IEEE Press Board Page Dedication Copyright Contents Before We Begin

  • Laws of Boolean Algebra

    This chapter contains sections titled: Sets of Axioms Perfect Induction Deduction Allowed Manipulations of Boolean Equations Principle of Duality

  • Number Systems and Counting

    This chapter contains sections titled: Numbers: Some Background The Decimal System: A Closer Look Other Bases Converting from Base 7 to Base 10 Converting from Base 10 to Base 7 Addition in Other Bases Counting The Binary Number System Combinatoric Examples

  • Combinational Circuits

    This chapter contains sections titled: Introduction to Digital Circuits Binary Numbers: a Quick Introduction Boolean Algebra Minterms: Standard or Canonical Sum of Products (SOP) Form Maxterms: Standard or Canonical Product of Sums (POS) Form Karnaugh Maps and Design Examples Product of Sums Simplifications Don't Care Conditions Logic Gates: Electrical and Timing Characteristics Summary Further Reading Problems

  • Interconnects for Digital Systems

    This chapter presents a treatment of the analysis and design of transmission line networks in digital systems. On¿¿¿chip lines are very lossy and the need to compact connections is also extremely important. On¿¿¿chip interconnects present an extreme situation and so the chapter is mostly focused on this situation. This situation has changed because of three main developments, primarily for digital circuits, but affecting analog circuitry because of mixed signal systems. The provision of signal return paths for digital and mixed signal chips has only been a recent consideration and then only for a few connections. The exceptions are clock distribution networks and other long connections where signal integrity is paramount. With RF and microwave chips there are relatively few active devices and so the provision of interconnects large enough and of defined ground planes for good current return paths can be accommodated at reasonable cost.

  • Digital Electronics

    This chapter contains sections titled: Introduction Circuit Board Material The Two-Sided Circuit Board Multilayer Circuit Boards Ground Planes and Digital Circuit Boards Clocked Logic The Transmission of a Single Logic Signal Decoupling Capacitors The Power Plane The Ground and Power Plane Capacitance Using Vias Decoupling Capacitors as Transmission Lines Characteristic Impedance Control Radiation from Digital Boards Measurement Problems - Ground Bounce High Clock Rates Balanced Transmission Ribbon Cable and Connectors Daughter Boards Mixing Analog and Digital Circuits Optical Isolation Gold Plating GHz Notes

  • Introduction to Digital Circuits

    In this chapter, synchronous design, which is commonly applied to most of the digital circuits, is introduced as a current key technology for realizing embedded systems.



Standards related to Digital Circuits

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No standards are currently tagged "Digital Circuits"