IEEE Organizations related to Yield-enhancement Redundancy

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Conferences related to Yield-enhancement Redundancy

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2013 Design, Automation & Test in Europe Conference & Exhibition (DATE 2013)

DATE is the complete event for the European electronic and test community. A leading world conference and exhibition, DATE unites 2,000 professionals with approximately 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.


2012 22nd International Conference on Field Programmable Logic and Applications (FPL)

Applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration of field programmable logic.



Periodicals related to Yield-enhancement Redundancy

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Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Instrumentation and Measurement, IEEE Transactions on

Measurements and instrumentation utilizing electrical and electronic techniques.


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.



Most published Xplore authors for Yield-enhancement Redundancy

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Xplore Articles related to Yield-enhancement Redundancy

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Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement

A. J. Yu; G. G. F. Lemieux International Conference on Field Programmable Logic and Applications, 2005., 2005

Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate multiple defects (Campregher et al., 2005). We propose a number of changes to the detailed routing architecture of island- style FPGAs to tolerate multiple random, distributed interconnect defects without ...


Fault-Tolerant ICs: The Reliability of TMR Yield-Enhanced ICs

Tim Haifley; Atul Bhatt IEEE Transactions on Reliability, 1987

The use of triple modular redundancy (TMR) for reliability enhancement is well known. This paper presents a simple method' for predicting the reliability of integrated circuits (ICs) which use TMR for yield enhancement. A simple yield- model is included as it is necessary to factor in the effect of consumption of redundancy paths due to wafer fabrication defects. TMR implementation ...


An approach for online repair and yield enhancement of VLSI/WSI redundant memories

Y. -N. Shen; F. Lombardi [1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications, 1991

A novel approach to yield enhancement of VLSI/WSI memories by row/column repair is presented. This approach is based on an online technique which executes concurrently with the testing process. The proposed repair approach consists of a divide-and-conquer strategy in which the overall fault pattern is divided into partitions. This is based on two practical considerations: the occurrence of faulty clusters ...


Defect-tolerant implementation of a systolic array for two-dimensional convolution

K. Ronner; V. Hecht; P. Pirsch 1991 Proceedings, International Conference on Wafer Scale Integration, 1991

A defect-tolerant, advanced VLSI-implementation of the two-dimensional convolution algorithm for real-time processing is presented. The chip contrasts with previously published convolution chips by its maximum mask size of 256 tabs (dividable into up to four independent masks which were applied to the same video-signal) support of adaptive filtering, on-chip delay-lines, and implemented special processing of frame-borders. Yield-enhancement techniques and architectural ...


Trading off area, yield and performance via hybrid redundancy in multi-core architectures

Yue Gao; Yang Zhang; Da Cheng; Melvin A. Breuer 2013 IEEE 31st VLSI Test Symposium (VTS), 2013

Manufacturing yield is a major concern for modern CMOS technologies. Fortunately, evolving chip architectures such as multi-cores have provided new venues for yield enhancement, and calls for a fresh perspective on the classic method of redundancy insertion. In this paper we outline a new approach towards redundancy insertion in modern multi-core CPU architectures. Traditionally, applying redundancy at a finer intra-core ...


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Educational Resources on Yield-enhancement Redundancy

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eLearning

Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement

A. J. Yu; G. G. F. Lemieux International Conference on Field Programmable Logic and Applications, 2005., 2005

Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate multiple defects (Campregher et al., 2005). We propose a number of changes to the detailed routing architecture of island- style FPGAs to tolerate multiple random, distributed interconnect defects without ...


Fault-Tolerant ICs: The Reliability of TMR Yield-Enhanced ICs

Tim Haifley; Atul Bhatt IEEE Transactions on Reliability, 1987

The use of triple modular redundancy (TMR) for reliability enhancement is well known. This paper presents a simple method' for predicting the reliability of integrated circuits (ICs) which use TMR for yield enhancement. A simple yield- model is included as it is necessary to factor in the effect of consumption of redundancy paths due to wafer fabrication defects. TMR implementation ...


An approach for online repair and yield enhancement of VLSI/WSI redundant memories

Y. -N. Shen; F. Lombardi [1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications, 1991

A novel approach to yield enhancement of VLSI/WSI memories by row/column repair is presented. This approach is based on an online technique which executes concurrently with the testing process. The proposed repair approach consists of a divide-and-conquer strategy in which the overall fault pattern is divided into partitions. This is based on two practical considerations: the occurrence of faulty clusters ...


Defect-tolerant implementation of a systolic array for two-dimensional convolution

K. Ronner; V. Hecht; P. Pirsch 1991 Proceedings, International Conference on Wafer Scale Integration, 1991

A defect-tolerant, advanced VLSI-implementation of the two-dimensional convolution algorithm for real-time processing is presented. The chip contrasts with previously published convolution chips by its maximum mask size of 256 tabs (dividable into up to four independent masks which were applied to the same video-signal) support of adaptive filtering, on-chip delay-lines, and implemented special processing of frame-borders. Yield-enhancement techniques and architectural ...


Trading off area, yield and performance via hybrid redundancy in multi-core architectures

Yue Gao; Yang Zhang; Da Cheng; Melvin A. Breuer 2013 IEEE 31st VLSI Test Symposium (VTS), 2013

Manufacturing yield is a major concern for modern CMOS technologies. Fortunately, evolving chip architectures such as multi-cores have provided new venues for yield enhancement, and calls for a fresh perspective on the classic method of redundancy insertion. In this paper we outline a new approach towards redundancy insertion in modern multi-core CPU architectures. Traditionally, applying redundancy at a finer intra-core ...


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Standards related to Yield-enhancement Redundancy

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