IEEE Organizations related to Yield-enhancement Redundancy

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Conferences related to Yield-enhancement Redundancy

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2013 Design, Automation & Test in Europe Conference & Exhibition (DATE 2013)

DATE is the complete event for the European electronic and test community. A leading world conference and exhibition, DATE unites 2,000 professionals with approximately 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.


2012 22nd International Conference on Field Programmable Logic and Applications (FPL)

Applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration of field programmable logic.



Periodicals related to Yield-enhancement Redundancy

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Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Instrumentation and Measurement, IEEE Transactions on

Measurements and instrumentation utilizing electrical and electronic techniques.


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.



Most published Xplore authors for Yield-enhancement Redundancy

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Xplore Articles related to Yield-enhancement Redundancy

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An approach for online repair and yield enhancement of VLSI/WSI redundant memories

Y. -N. Shen; F. Lombardi CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings., 1991

A novel approach to yield enhancement of VLSI/WSI memories by row/column repair is presented. This approach is based on an online technique which executes concurrently with the testing process. The proposed repair approach consists of a divide-and-conquer strategy in which the overall fault pattern is divided into partitions. This is based on two practical considerations: the occurrence of faulty clusters ...


Redundancy Reliability

Dwight L. Crook; William K. Meyer Reliability Physics Symposium, 1981. 19th Annual, 1981

Programmable redundant row and column elements are presently being used as a yield enhancement tool on the more advanced high density memory devices. This paper summarizes a comprehensive reliability study which was conducted to insure acceptable reliability standards on products using redundancy. Data on fuse programming are presented which indicate acceptable fuse reliability. Also, data are presented which show that ...


A hierarchical redundant cube-connected cycle for WSI yield enhancement

S. Horiguchi; S. Fukuda Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on, 1995

To enhance system yield for a large scale cube-connected cycle (CCC), we propose a hierarchical redundant architecture in which a cycle is implemented on two rows at the first level and all cycles at the first level are connected as a block in a two dimensional array at the second level. The hierarchical architecture proposed is investigated in area performance ...


A fast 16K static RAM built with a silicide enhanced NMOS process

B. A. Frederick IEEE Journal of Solid-State Circuits, 1983

A 25-ns 16K RAM is described which uses internal asynchronous precharging, a unique column buffer, and latching data lines. The NMOS technology features are 1.3 /spl mu/ L/SUB eff/, molybdenum silicide interconnect, and laser redundancy for yield enhancement.


Optimizing reliability in a two-level distributed architecture for wafer scale integration

J. R. Samson Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on, 1994

Fault tolerance to support mission life reliability is a key consideration in many system applications. Redundancy for defect tolerance, i.e., yield enhancement, and wafer-level reliability enhancement have been standard practice since the advent of wafer scale technology. The Reliability-Hardware Quotient (RHQ) is an example of a fundamental composite metric which is useful for identifying the optimal design point in a ...


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Educational Resources on Yield-enhancement Redundancy

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eLearning

An approach for online repair and yield enhancement of VLSI/WSI redundant memories

Y. -N. Shen; F. Lombardi CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings., 1991

A novel approach to yield enhancement of VLSI/WSI memories by row/column repair is presented. This approach is based on an online technique which executes concurrently with the testing process. The proposed repair approach consists of a divide-and-conquer strategy in which the overall fault pattern is divided into partitions. This is based on two practical considerations: the occurrence of faulty clusters ...


Redundancy Reliability

Dwight L. Crook; William K. Meyer Reliability Physics Symposium, 1981. 19th Annual, 1981

Programmable redundant row and column elements are presently being used as a yield enhancement tool on the more advanced high density memory devices. This paper summarizes a comprehensive reliability study which was conducted to insure acceptable reliability standards on products using redundancy. Data on fuse programming are presented which indicate acceptable fuse reliability. Also, data are presented which show that ...


A hierarchical redundant cube-connected cycle for WSI yield enhancement

S. Horiguchi; S. Fukuda Wafer Scale Integration, 1995. Proceedings., Seventh Annual IEEE International Conference on, 1995

To enhance system yield for a large scale cube-connected cycle (CCC), we propose a hierarchical redundant architecture in which a cycle is implemented on two rows at the first level and all cycles at the first level are connected as a block in a two dimensional array at the second level. The hierarchical architecture proposed is investigated in area performance ...


A fast 16K static RAM built with a silicide enhanced NMOS process

B. A. Frederick IEEE Journal of Solid-State Circuits, 1983

A 25-ns 16K RAM is described which uses internal asynchronous precharging, a unique column buffer, and latching data lines. The NMOS technology features are 1.3 /spl mu/ L/SUB eff/, molybdenum silicide interconnect, and laser redundancy for yield enhancement.


Optimizing reliability in a two-level distributed architecture for wafer scale integration

J. R. Samson Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on, 1994

Fault tolerance to support mission life reliability is a key consideration in many system applications. Redundancy for defect tolerance, i.e., yield enhancement, and wafer-level reliability enhancement have been standard practice since the advent of wafer scale technology. The Reliability-Hardware Quotient (RHQ) is an example of a fundamental composite metric which is useful for identifying the optimal design point in a ...


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