IEEE Organizations related to Yield-enhancement Redundancy

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Conferences related to Yield-enhancement Redundancy

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2013 Design, Automation & Test in Europe Conference & Exhibition (DATE 2013)

DATE is the complete event for the European electronic and test community. A leading world conference and exhibition, DATE unites 2,000 professionals with approximately 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.


2012 22nd International Conference on Field Programmable Logic and Applications (FPL)

Applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration of field programmable logic.



Periodicals related to Yield-enhancement Redundancy

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Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Dependable and Secure Computing, IEEE Transactions on

The purpose of TDSC is to publish papers in dependability and security, including the joint consideration of these issues and their interplay with system performance. These areas include but are not limited to: System Design: architecture for secure and fault-tolerant systems; trusted/survivable computing; intrusion and error tolerance, detection and recovery; fault- and intrusion-tolerant middleware; firewall and network technologies; system management ...


Instrumentation and Measurement, IEEE Transactions on

Measurements and instrumentation utilizing electrical and electronic techniques.


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.



Most published Xplore authors for Yield-enhancement Redundancy

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Xplore Articles related to Yield-enhancement Redundancy

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Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model

D. D. Sharma; F. J. Meyer; D. K. Pradhan IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993

To determine the optimal redundancy organization for yield enhancement, redundant and modular memories are analyzed using the center-satellite model. The model suggests that the degree of redundancy for a memory module be determined according to its distance from the periphery of the wafer since the defect density increases as the periphery is neared. Analytical expressions are formulated for the yield ...


A hierarchical redundant cube-connected cycle for WSI yield enhancement

S. Horiguchi; S. Fukuda Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI), 1995

To enhance system yield for a large scale cube-connected cycle (CCC), we propose a hierarchical redundant architecture in which a cycle is implemented on two rows at the first level and all cycles at the first level are connected as a block in a two dimensional array at the second level. The hierarchical architecture proposed is investigated in area performance ...


Yield enhancement of field programmable logic arrays by inherent component redundancy

M. Demjanenko; S. J. Upadhyaya IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990

A complete technique that does not use any additional components for enhancing the yield of field-programmable logic arrays (FPLAs) is presented. In this approach, the inherent sparsity (absence of devices at crosspoints) of programmable logic arrays (PLAs) is utilized to mask certain types of manufacturing defects within the unprogrammed FPLAs, thus reclaiming chips which are otherwise discarded. Two categories of ...


Dynamic yield analysis and enhancement of FPGA reconfigurable memory system

M. Choi; N. Park IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188), 2001

This paper discusses the issues of FPGA reconfigurable memory system with faulty physical memory cells and yield measurement techniques are proposed. Static yield and dynamic yield of FPGA reconfigurable memory systems and their characteristics are analyzed. Yield enhancement of conventional memory systems relies on additional redundancy, but FPGA reconfigurable memory systems have inherited redundancy and customizability. Thus, they can accommodate ...


A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond

T. Yamagata; H. Sato; K. Fujita; Y. Nishimura; K. Anami IEEE Journal of Solid-State Circuits, 1996

This paper describes a distributed globally replaceable redundancy (DGR) scheme which achieves a higher optimization of the trade-off between yield enhancement and chip area penalty. A newly developed yield simulator using the Monte Carlo method has estimated the effectiveness of the DGR scheme in a quantitative manner. The new redundancy scheme is expected to enhance the yield by several times ...


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Educational Resources on Yield-enhancement Redundancy

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eLearning

Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model

D. D. Sharma; F. J. Meyer; D. K. Pradhan IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993

To determine the optimal redundancy organization for yield enhancement, redundant and modular memories are analyzed using the center-satellite model. The model suggests that the degree of redundancy for a memory module be determined according to its distance from the periphery of the wafer since the defect density increases as the periphery is neared. Analytical expressions are formulated for the yield ...


A hierarchical redundant cube-connected cycle for WSI yield enhancement

S. Horiguchi; S. Fukuda Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI), 1995

To enhance system yield for a large scale cube-connected cycle (CCC), we propose a hierarchical redundant architecture in which a cycle is implemented on two rows at the first level and all cycles at the first level are connected as a block in a two dimensional array at the second level. The hierarchical architecture proposed is investigated in area performance ...


Yield enhancement of field programmable logic arrays by inherent component redundancy

M. Demjanenko; S. J. Upadhyaya IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990

A complete technique that does not use any additional components for enhancing the yield of field-programmable logic arrays (FPLAs) is presented. In this approach, the inherent sparsity (absence of devices at crosspoints) of programmable logic arrays (PLAs) is utilized to mask certain types of manufacturing defects within the unprogrammed FPLAs, thus reclaiming chips which are otherwise discarded. Two categories of ...


Dynamic yield analysis and enhancement of FPGA reconfigurable memory system

M. Choi; N. Park IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188), 2001

This paper discusses the issues of FPGA reconfigurable memory system with faulty physical memory cells and yield measurement techniques are proposed. Static yield and dynamic yield of FPGA reconfigurable memory systems and their characteristics are analyzed. Yield enhancement of conventional memory systems relies on additional redundancy, but FPGA reconfigurable memory systems have inherited redundancy and customizability. Thus, they can accommodate ...


A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond

T. Yamagata; H. Sato; K. Fujita; Y. Nishimura; K. Anami IEEE Journal of Solid-State Circuits, 1996

This paper describes a distributed globally replaceable redundancy (DGR) scheme which achieves a higher optimization of the trade-off between yield enhancement and chip area penalty. A newly developed yield simulator using the Monte Carlo method has estimated the effectiveness of the DGR scheme in a quantitative manner. The new redundancy scheme is expected to enhance the yield by several times ...


More eLearning Resources

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Standards related to Yield-enhancement Redundancy

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Jobs related to Yield-enhancement Redundancy

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