IEEE Organizations related to Yield-enhancement Redundancy

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Conferences related to Yield-enhancement Redundancy

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2013 Design, Automation & Test in Europe Conference & Exhibition (DATE 2013)

DATE is the complete event for the European electronic and test community. A leading world conference and exhibition, DATE unites 2,000 professionals with approximately 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.

2012 22nd International Conference on Field Programmable Logic and Applications (FPL)

Applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration of field programmable logic.

Periodicals related to Yield-enhancement Redundancy

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Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...

Instrumentation and Measurement, IEEE Transactions on

Measurements and instrumentation utilizing electrical and electronic techniques.

Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.

Xplore Articles related to Yield-enhancement Redundancy

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Quality enhancement of reconfigurable multichip module systems by redundancy utilization

Minsu Choi; Nohpill Park; Lombardi, Fabrizio; Piuri, V. Instrumentation and Measurement, IEEE Transactions on, 2002

This paper evaluates the quality effectiveness of redundancy utilization in reconfigurable multichip mode (RMCM) systems. Due to reconfigurability, the RMCM system can implement a device with different redundancy levels. A redundancy level is determined by the requirement of fault tolerance (FT) of the device under implementation which can be realized through reconfiguration. No previous work has adequately investigated the effect ...

A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories

Changwook Lee; Wooheon Kang; Donkoo Cho; Sungho Kang Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2014

3-D-stacked memory using through-silicon-vias (TSVs) has emerged as a good alternative for overcoming the limitation of 2-D memory technology. Among many issues with 3-D-stacked memory, yield is one of the major challenges for mass production. This paper proposes a new fuse architecture and redundancy scheme to improve the yield of 3-D-stacked memories. The new fuse architecture is developed based on ...

Trading off area, yield and performance via hybrid redundancy in multi-core architectures

Yue Gao; Yang Zhang; Da Cheng; Breuer, M.A. VLSI Test Symposium (VTS), 2013 IEEE 31st, 2013

Manufacturing yield is a major concern for modern CMOS technologies. Fortunately, evolving chip architectures such as multi-cores have provided new venues for yield enhancement, and calls for a fresh perspective on the classic method of redundancy insertion. In this paper we outline a new approach towards redundancy insertion in modern multi-core CPU architectures. Traditionally, applying redundancy at a finer intra-core ...

Redundancy for yield enhancement in the 3-D computer

Yung, M.W.; Little, M.J.; Etchells, R.D.; Nash, J.G. Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on, 1989

A prototype 3-D Computer which demonstrates the feasibility of the stacked wafer approach is discussed. The wafer-scale integrated circuits of the 3-D Computer have been carefully partitioned to enable redundancy to be used to insure high yields. Redundancy approaches, implementation issues, and testability both for the schemes used in the prototype and in future generations of the 3-D Computer are ...

Yield optimization in large RAM's with hierarchical redundancy

Ganapathy, K.N.; Singh, A.D.; Pradhan, D.K. Solid-State Circuits, IEEE Journal of, 1991

The authors present and analyze large RAM architectures with hierarchical redundancy and determine the optimal redundancy organization for yield enhancement. A two-level redundancy scheme is used for defect tolerance, and the defect distribution is modeled using the compounded Poisson model. The tree random access memory (TRAM), which has been proposed as a design methodology for future multimegabit memories (N. Jarwala ...

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Educational Resources on Yield-enhancement Redundancy

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