IEEE Organizations related to Yield-enhancement Redundancy

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Conferences related to Yield-enhancement Redundancy

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2013 Design, Automation & Test in Europe Conference & Exhibition (DATE 2013)

DATE is the complete event for the European electronic and test community. A leading world conference and exhibition, DATE unites 2,000 professionals with approximately 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.


2012 22nd International Conference on Field Programmable Logic and Applications (FPL)

Applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration of field programmable logic.



Periodicals related to Yield-enhancement Redundancy

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Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Instrumentation and Measurement, IEEE Transactions on

Measurements and instrumentation utilizing electrical and electronic techniques.


Solid-State Circuits, IEEE Journal of

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as device modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete ...


Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Integrated circuits and systems;VLSI based Architecture and applications; highspeed circuits and interconnect; mixed-signal SoC; speed/area/power/noise tradeoffs in CMOS circuits.



Most published Xplore authors for Yield-enhancement Redundancy

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Xplore Articles related to Yield-enhancement Redundancy

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Yield enhancement of digital microfluidics-based biochips using space redundancy and local reconfiguration

Fei Su; K. Chakrabarty; V. K. Pamula Design, Automation and Test in Europe, 2005

As microfluidics-based biochips become more complex, manufacturing yield will have significant influence on production volume and product cost. We propose an interstitial redundancy approach to enhance the yield of biochips that are based on droplet-based microfluidics. In this design method, spare cells are placed in the interstitial sites within the microfluidic array, and they replace neighboring faulty cells via local ...


Spare cutting approaches for repairing memories

Y. -N. Shen; N. Park; F. Lombardi Proceedings International Conference on Computer Design. VLSI in Computers and Processors, 1996

This paper presents new algorithms for yield enhancement of redundant memories. These algorithms are based on the technique of spare cutting for a redundant memory chip in which repair is implemented by row/column deletion. Different approaches are proposed: some of these approaches are based on a fully exhaustive process, while others try to heuristically reduce the computational overhead involved in ...


Multilevel Routing With Redundant Via Insertion

H. Yao; Y. Cai; Q. Zhou; X. Hong IEEE Transactions on Circuits and Systems II: Express Briefs, 2006

This brief presents an improved multilevel full-chip routing system which integrates the redundant via placement in the routing flow for yield and reliability enhancement. The system features a pre-coarsening stage which is equipped with fast congestion-driven L-pattern global router followed by detailed router. The L-pattern global routing benefits to the reduction of vias and thus relieves the burden of redundant ...


Redundancy for yield enhancement in the 3-D computer

M. W. Yung; M. J. Little; R. D. Etchells; J. G. Nash [1989] Proceedings International Conference on Wafer Scale Integration, 1989

A prototype 3-D Computer which demonstrates the feasibility of the stacked wafer approach is discussed. The wafer-scale integrated circuits of the 3-D Computer have been carefully partitioned to enable redundancy to be used to insure high yields. Redundancy approaches, implementation issues, and testability both for the schemes used in the prototype and in future generations of the 3-D Computer are ...


Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement

A. J. Yu; G. G. F. Lemieux International Conference on Field Programmable Logic and Applications, 2005., 2005

Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate multiple defects (Campregher et al., 2005). We propose a number of changes to the detailed routing architecture of island- style FPGAs to tolerate multiple random, distributed interconnect defects without ...


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Educational Resources on Yield-enhancement Redundancy

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eLearning

Yield enhancement of digital microfluidics-based biochips using space redundancy and local reconfiguration

Fei Su; K. Chakrabarty; V. K. Pamula Design, Automation and Test in Europe, 2005

As microfluidics-based biochips become more complex, manufacturing yield will have significant influence on production volume and product cost. We propose an interstitial redundancy approach to enhance the yield of biochips that are based on droplet-based microfluidics. In this design method, spare cells are placed in the interstitial sites within the microfluidic array, and they replace neighboring faulty cells via local ...


Spare cutting approaches for repairing memories

Y. -N. Shen; N. Park; F. Lombardi Proceedings International Conference on Computer Design. VLSI in Computers and Processors, 1996

This paper presents new algorithms for yield enhancement of redundant memories. These algorithms are based on the technique of spare cutting for a redundant memory chip in which repair is implemented by row/column deletion. Different approaches are proposed: some of these approaches are based on a fully exhaustive process, while others try to heuristically reduce the computational overhead involved in ...


Multilevel Routing With Redundant Via Insertion

H. Yao; Y. Cai; Q. Zhou; X. Hong IEEE Transactions on Circuits and Systems II: Express Briefs, 2006

This brief presents an improved multilevel full-chip routing system which integrates the redundant via placement in the routing flow for yield and reliability enhancement. The system features a pre-coarsening stage which is equipped with fast congestion-driven L-pattern global router followed by detailed router. The L-pattern global routing benefits to the reduction of vias and thus relieves the burden of redundant ...


Redundancy for yield enhancement in the 3-D computer

M. W. Yung; M. J. Little; R. D. Etchells; J. G. Nash [1989] Proceedings International Conference on Wafer Scale Integration, 1989

A prototype 3-D Computer which demonstrates the feasibility of the stacked wafer approach is discussed. The wafer-scale integrated circuits of the 3-D Computer have been carefully partitioned to enable redundancy to be used to insure high yields. Redundancy approaches, implementation issues, and testability both for the schemes used in the prototype and in future generations of the 3-D Computer are ...


Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement

A. J. Yu; G. G. F. Lemieux International Conference on Field Programmable Logic and Applications, 2005., 2005

Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate multiple defects (Campregher et al., 2005). We propose a number of changes to the detailed routing architecture of island- style FPGAs to tolerate multiple random, distributed interconnect defects without ...


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Standards related to Yield-enhancement Redundancy

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