Conferences related to Yield-enhancement Redundancy

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2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

PRIME2017 conference program will reflect the wide spectrum of research topics in Microelectronics and Electronics, building bridges between various research fields. PRIME has been established over the recent years as an important conference where Ph.D. students and post-docs with less than one year post-Pd.D. experience can present their research results and network with experts from industry, academia and research. The main objectives of PRIME are: to encourage favourable exposure to Ph. D. students in the early stages of their careers; to benchmark Ph.D. research in a friendly and cooperative environment; to enable sharing of student and supervisor experiences of scientific and engineering research; to connect Ph.d. students and their supervisors with companies and research centres.

  • 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    PRIME2016 conference program will reflect the wide spectrum of research topics in Microelectronics and Electronics, building bridges between various research fields. PRIME has been established over the recent years as an important conference where PhD students and post-docs with less than one year post-PhD experience can present their research results and network with experts from industry, academia and research. The main objectives of PRIME are: to encourage favourable exposure to Ph.D. students in the early stages of their careers; to benchmark Ph.D. research in a friendly and cooperative environment; to enable sharing of student and supervisor experiences of scientific and engineering research; to connect Ph.D. students and their supervisors with companies and research centres.

  • 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    PRIME conference is dedicated to Ph. D. students who have to present all regular papers.The purpose of PRIME is to: Encourage favorable exposure to Ph. D. students in the early stage of their career, Benchmark Ph. D. research in a friendly and cooperative environment, Enable sharing of Ph. D. and supervisors experience on scientific research, Create a connection between academic world and companies to meet these expectations PRIME features: Conference program reflecting the wide spectrum of research topics in Microelectronics and Electronics, building bridges between research fields, Free of charge full-day tutorials for all conference participants, Company Fair for fruitful interactions between Ph.D. students and their supervisors with industry representatives

  • 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    PRIME conference is dedicated to Ph. D. students who have to present all regular papers.The purpose of PRIME is to :- Encourage favorable exposure to Ph. D. students in the early stage of their career- Benchmark Ph. D. research in a friendly and cooperative environment- Enable sharing of Ph. D. and supervisors experience on scientific research- Create a connection between academic world and companiesTo meet these expectations PRIME features:- Conference program reflecting the wide spectrum of research topics in Microelectronics and Electronics, building bridges between research fields- Free of charge full-day tutorials for all conference participants- Company Fair for fruitful interactions between Ph.D. students and their supervisors with industry representatives

  • 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    The conference is a meeting point for PhD students that have the opportunity to present their scientific activities.

  • 2012 8th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    Encourage publication by Ph.D. students in the early stages of their career, in order to benchmark there research in a friendly and cooperative environment. Enable sharing of scientific and engineering experiences between students and supervisors.

  • 2011 7th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

    The objectives of PRIME are: - to encourage favourable exposure to Ph. D. students in the early stages of their careers; - to benchmark Ph.D. research in a friendly and cooperative environment; - to enable sharing of students and supervisors experiences of scientific and engineering research; - to connect Ph.D. students and their supervisors with companies and research centers.

  • 2010 Ph.D. Research in Microelectronics and Electronics (PRIME)

    Last year P.hD. candidates should be come together at PRIME 2010 to be networked with Industry

  • 2009 Ph.D. Research in Microelectronics and Electronics (PRIME)

    The objectives of PRIME are: to encourage favourable exposure to Ph.D. students in the early stages of their careers, to benchmark Ph.D. research in a friendly and cooperative environment, to enable sharing of students and supervisors experiences of scientific and engineering research, and to connect Ph.D. students and their supervisors with companies and research centres.

  • 2008 Ph.D. Research in Microelectronics and Electronics (PRIME)

    The purpose of this conference is to: # Encourage favourable exposure to Ph.D. students in the early stage of their career # Benchmark Ph.D. research in a friendly and cooperative environement # Enable sharing of Ph.D. and supervisors experience on scientific research # Create at the Company Fair a connection between academic world (Ph.D. students) and companies The aim of PRIME 2008 is to provide an opportunity for Ph.D. students to present their research activity and contact other people in the rese

  • 2007 Ph.D. Research in Microelectronics and Electronics (PRIME)

    The purpose of this conference is to encourage favourable exposure to Ph.D. students in the early stage of their career and to benchmark Ph.D. research in a friendly and cooperative environment. It will also enable sharing of Ph.D. and supervisors experience on scientific research and create at the Company Fair a connection between academic world (Ph.D. students) and companies.

  • 2006 Ph.D. Research in Microelectronics and Electronics (PRIME)

  • 2005 Ph.D. Research in Microelectronics and Electronics (PRIME)


2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)

ASP-DAC 2017 is the twenty-second annual international conference on VLSI design automation in Asia and South Pacific region, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.


2017 22nd IEEE European Test Symposium (ETS)

The scope of the conference is electronic-based circuits and system testing, including VLSI Test, VLSI Reliability, Yield, diagnosis, DFX, Verification, etc.


2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

The 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS) will be held in Batumi, Georgia on December 5-8, 2017. As the flagship conference of IEEE Circuits and Systems Society in Region 8 of IEEE (Europe, Middle East, and Africa), ICECS 2017 will consist of tutorials, plenary lectures, regular, special and poster sessions focusing on recent trends, emerging technologies and advances in all aspects of:¿ Circuits ¿ Systems ¿ Signals ¿ Mathematical Methods ¿ Computational Methods ¿ Applications


2017 27th International Conference on Field Programmable Logic and Applications (FPL)

The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing. The conference objective is to bring together researchers and practitioners from both academia and industry and from around the world. FPL 2017 will offer the following five conference tracks: Architectures and Technology; Applications and Benchmarks; Design Methods and Tools; Self-aware and Adaptive Systems; Surveys, Trends and Education.

  • 2016 26th International Conference on Field Programmable Logic and Applications (FPL)

    The International Conference on Field Programmable Logic and Applications (FPL) is the firstand largest conference covering the rapidly growing area of field-programmable logic. Duringthe past 26 years, many of the advances achieved in reconfigurable system architectures,applications, embedded processors, design automation methods (EDA) and tools have beenfirst published in the proceedings of the FPL conference series. FPL 2016 will offer the followingfive conference tracks: Architectures and Technology, Applications and Benchmarks, DesignMethods and Tools, Self-aware and Adaptive Systems, Surveys, Trends and Education

  • 2015 25th International Conference on Field Programmable Logic and Applications (FPL)

    The International Conference on Field Programmable Logic and Applications (FPL) is the first and largest conference covering the rapidly growing area of field-programmable logic. During the past 25 years, many of the advances achieved in reconfigurable system architectures, applications, embedded processors, design automation methods (EDA) and tools have been first published in the proceedings of the FPL conference series. FPL 2015 plans to gear a technical focus towards: “Power efficient and self-aware FPGA accelerators and heterogeneous computing platforms for HPC and embedded / cyber physical systems”. Highlights of FPL 2015 will include industry keynotes. FPL 2015 will offer the following five conference tracks: Architectures and Technology, Applications and Benchmarks, Design Methods and Tools, Self-aware and Adaptive Systems, Surveys, Trends and Education

  • 2014 24th International Conference on Field Programmable Logic and Applications (FPL)

    The International Conference on Field Programmable Logic and Applications (FPL) is the first and largest conference covering the rapidly growing area of field-programmable logic. During the past 23 years, many of the advances achieved in reconfigurable system architectures, applications, embedded processors, design automation methods (EDA) and tools have been first published in the proceedings of the FPL conference series. Its objective is to bring together researchers and practitioners from both academia and industry from all over the world.A special focus for FPL 2014 shall be on dependable, power efficient FPGA accelerators and heterogeneous computing platforms for HPC and embedded / cyber physical systems. Submissions shall be categorized into the following four tracks: Architectures and Technology, Applications and Benchmarks, Design Methods and Tools, Surveys, Trends and Education.

  • 2013 23rd International Conference on Field Programmable Logic and Applications (FPL)

    The objective of FPL is to bring together researchers and industry from all over the world for a wide ranging discussion on FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration.The conference topics include, but are not limited to: Architectures; Design Methods and Tools; Applications (aerospace and automotive, bioinformatics, finance, medical, security); Surveys, Trends and Education.

  • 2012 22nd International Conference on Field Programmable Logic and Applications (FPL)

    Applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration of field programmable logic.

  • 2011 International Conference on Field Programmable Logic and Applications (FPL)

    FPL is the first and largest conference covering the rapidly growing area of field-programmable logic. Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion on FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, and dynamic reconfiguration.

  • 2010 International Conference on Field Programmable Logic and Applications (FPL)

    The conference objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs and other field-programmable devices, their architectures and design methods, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2009 International Conference on Field Programmable Logic and Applications (FPL)

    The conference objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs and other field-programmable devices, their architectures and design methods, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2008 International Conference on Field Programmable Logic and Applications (FPL)

    Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2007 International Conference on Field Programmable Logic and Applications (FPL)

    Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

  • 2006 International Conference on Field Programmable Logic and Applications (FPL)

  • 2005 International Conference on Field Programmable Logic and Applications (FPL)


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Periodicals related to Yield-enhancement Redundancy

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Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Dependable and Secure Computing, IEEE Transactions on

The purpose of TDSC is to publish papers in dependability and security, including the joint consideration of these issues and their interplay with system performance. These areas include but are not limited to: System Design: architecture for secure and fault-tolerant systems; trusted/survivable computing; intrusion and error tolerance, detection and recovery; fault- and intrusion-tolerant middleware; firewall and network technologies; system management ...


Design & Test of Computers, IEEE

IEEE Design & Test of Computers offers original works describing the methods used to design and test electronic product hardware and supportive software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. Topics include IC/module design, low-power design, electronic design automation, design/test verification, practical technology, and standards. IEEE Design & Test of ...


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Most published Xplore authors for Yield-enhancement Redundancy

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Xplore Articles related to Yield-enhancement Redundancy

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Efficient reconfiguration algorithms for degradable VLSI/WSI arrays

S. -Y. Kuo; I. -Y. Chen 1991 Proceedings, International Conference on Wafer Scale Integration, 1991

A systematic method for reconfiguration in VLSI/WSI (wafer scale integration) arrays using the degradation approach for yield enhancement is presented. Based on the bipartite graph representation of faulty cells in a reconfigurable host array, the problem of finding a maximum fault-free target array is shown to be equivalent to finding a restricted independent set of vertices in the graph models. ...


Leakage-aware redundancy for reliable sub-threshold memories

Seokjoong Kim; Matthew Guthaus 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011

In this work, we are the first to consider the optimization of sub-threshold stand-by VDD while simultaneously considering memory yield and redundant row/column usage. We propose a fast, optimal fault-repair analysis framework that is 200-600% faster than previous works and show that leakage can be reduced 10-14% using redundancy without sacrificing yield.


Redundancy Reliability

Dwight L. Crook; William K. Meyer 19th International Reliability Physics Symposium, 1981

Programmable redundant row and column elements are presently being used as a yield enhancement tool on the more advanced high density memory devices. This paper summarizes a comprehensive reliability study which was conducted to insure acceptable reliability standards on products using redundancy. Data on fuse programming are presented which indicate acceptable fuse reliability. Also, data are presented which show that ...


Yield enhancement of field programmable logic arrays by inherent component redundancy

M. Demjanenko; S. J. Upadhyaya IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990

A complete technique that does not use any additional components for enhancing the yield of field-programmable logic arrays (FPLAs) is presented. In this approach, the inherent sparsity (absence of devices at crosspoints) of programmable logic arrays (PLAs) is utilized to mask certain types of manufacturing defects within the unprogrammed FPLAs, thus reclaiming chips which are otherwise discarded. Two categories of ...


On Yield Consideration for the Design of Redundant Programmable Logic Arrays

Chin-Long Wey 24th ACM/IEEE Design Automation Conference, 1987

This paper presents the design of a programmable logic array with redundancy. The design allows for the repair of a defective chip by including the redundancy circuits to a conventional PLA. When the redundancy technique is implemented into the VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area. Indeed, the additional spare lines ...


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Educational Resources on Yield-enhancement Redundancy

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eLearning

Efficient reconfiguration algorithms for degradable VLSI/WSI arrays

S. -Y. Kuo; I. -Y. Chen 1991 Proceedings, International Conference on Wafer Scale Integration, 1991

A systematic method for reconfiguration in VLSI/WSI (wafer scale integration) arrays using the degradation approach for yield enhancement is presented. Based on the bipartite graph representation of faulty cells in a reconfigurable host array, the problem of finding a maximum fault-free target array is shown to be equivalent to finding a restricted independent set of vertices in the graph models. ...


Leakage-aware redundancy for reliable sub-threshold memories

Seokjoong Kim; Matthew Guthaus 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011

In this work, we are the first to consider the optimization of sub-threshold stand-by VDD while simultaneously considering memory yield and redundant row/column usage. We propose a fast, optimal fault-repair analysis framework that is 200-600% faster than previous works and show that leakage can be reduced 10-14% using redundancy without sacrificing yield.


Redundancy Reliability

Dwight L. Crook; William K. Meyer 19th International Reliability Physics Symposium, 1981

Programmable redundant row and column elements are presently being used as a yield enhancement tool on the more advanced high density memory devices. This paper summarizes a comprehensive reliability study which was conducted to insure acceptable reliability standards on products using redundancy. Data on fuse programming are presented which indicate acceptable fuse reliability. Also, data are presented which show that ...


Yield enhancement of field programmable logic arrays by inherent component redundancy

M. Demjanenko; S. J. Upadhyaya IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990

A complete technique that does not use any additional components for enhancing the yield of field-programmable logic arrays (FPLAs) is presented. In this approach, the inherent sparsity (absence of devices at crosspoints) of programmable logic arrays (PLAs) is utilized to mask certain types of manufacturing defects within the unprogrammed FPLAs, thus reclaiming chips which are otherwise discarded. Two categories of ...


On Yield Consideration for the Design of Redundant Programmable Logic Arrays

Chin-Long Wey 24th ACM/IEEE Design Automation Conference, 1987

This paper presents the design of a programmable logic array with redundancy. The design allows for the repair of a defective chip by including the redundancy circuits to a conventional PLA. When the redundancy technique is implemented into the VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area. Indeed, the additional spare lines ...


More eLearning Resources

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Standards related to Yield-enhancement Redundancy

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