Conferences related to Transistors

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2017 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

  • 2021 IEEE International Electron Devices Meeting (IEDM)

    the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

  • 2019 IEEE International Electron Devices Meeting (IEDM)

    the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

  • 2015 IEEE International Electron Devices Meeting (IEDM)

    the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart-power technologies, etc.

  • 2014 IEEE International Electron Devices Meeting (IEDM)

    IEDM is the world s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.

  • 2013 IEEE International Electron Devices Meeting (IEDM)

    IEDM is the world s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.

  • 2012 IEEE International Electron Devices Meeting (IEDM)

  • 2011 IEEE International Electron Devices Meeting (IEDM)

    CMOS Devices Technology, Characterization, Reliability and Yield, Displays, sensors and displays, memory technology, modeling and simulation, process technology, solid state and nanoelectronic devices.

  • 2010 IEEE International Electron Devices Meeting (IEDM)

  • 2009 IEEE International Electron Devices Meeting (IEDM)

    CMOS Devices Technology, Characterization, REliability and Yield, Displays, sensors and displays, memory technology, modeling and simulation, process technology, solid state and nanoelectronic devices

  • 2008 IEEE International Electron Devices Meeting (IEDM)

    Over the last 53 years, the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart-power technologies, etc.

  • 2007 IEEE International Electron Devices Meeting (IEDM)

  • 2006 IEEE International Electron Devices Meeting (IEDM)


2013 IEEE International Integrated Reliability Workshop (IIRW)

We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: resistive memories, high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, root cause defects (physical mechanisms and simulations), Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, designing-in reliability (products, circuits,systems, processes), customer product reliability requirements / manufacturer reliability tasks, waferlevel reliability tests (test approaches and reliability test structures), reliability modeling and simulation,optoelectronics, and single event upsets.

  • 2012 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.

  • 2011 IEEE International Integrated Reliability Workshop (IIRW)

    The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems through tutorials, paper presentations, discussion groups and special interest groups.

  • 2010 IEEE International Integrated Reliability Workshop (IIRW)

    The Integrated Reliability Workshop focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and f

  • 2009 IEEE International Integrated Reliability Workshop (IRW)

    Semiconductor Reliability in general; and Wafer Level Reliability in specific. Covering areas like (but not limited to): Design-in Reliability, reliability characterization, deep sub-micron transistor and circuit reliability, customer reliability requirements, wafer level reliability tests, and reliability root cause analysis, etc.


2012 19th Biennial University/Government/Industry Micro/Nano Symposium (UGIM)

The goal of this symposium is to bring together educators and researchers around the world involved in academic laboratory development and management, and to provide a forum for exchanging information and presenting new research and educational concepts.



Periodicals related to Transistors

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Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Microwave Magazine, IEEE

Focuses on applications of technical knowledge. IEEE Microwave Magazine concentrates on general-interest, applications-oriented articles as well as technical articles in the field of microwave theory and techniques including components, devices, circuits, and systems involving the generation, modulation, demodulation, control, transmission and detection of microwaves.


Nanotechnology, IEEE Transactions on

The proposed IEEE Transactions on Nanotechnology will be devoted to the publication of manuscripts of archival value in the general area of nanotechnology, that is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.


Nuclear Science, IEEE Transactions on

All aspects of the theory and applications of nuclear science and engineering, including instrumentation for the detection and measurement of ionizing radiation; particle accelerators and their controls; nuclear medicine and its application; effects of radiation on materials, components, and systems; reactor instrumentation and controls; and measurement of radiation in space.




Xplore Articles related to Transistors

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15th Annual NEC to have 28 technical sessions, 260 exhibits

Electrical Engineering, 1959

None


A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters

Michael Pehl; Tobias Massier; Helmut Graeb; Ulf Schlichtmann 2008 IEEE International Conference on Computer Design, 2008

Many methods for analog circuit sizing are available as commercial, in-house and academic tools. They are based on continuous optimization, e.g., of transistor geometries, although the subsequent layout step requires values on a pre-defined grid. In addition, sizing of transistors for bipolar and RF circuits frequently necessitates the use of multiples of predefined values for the design parameters. This paper ...


Comparison of DI and JI lateral IGBTs

Y. S. Huang; B. J. Baliga; S. Tandon; A. Reisman Proceedings of the 4th International Symposium on Power Semiconductor Devices and Ics, 1992

First Page of the Article ![](/xploreAssets/images/absImages/00991234.png)


Buffer allocation algorithm with consideration of routing congestion

Yuchun Ma; Xianiong Hong; Sheqin Dong; Song Chen; Yici Cai; Chung-Kuan Cheng; Jun Gu ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 2004

The dominating contribution of interconnect to system performance has made it critical to plan the buffers and the routes resource in the early stage of the layout. In this paper, we present a congestion estimation model which takes the buffer insertion sites into consideration. Based on the feasible region of the buffer insertion, the two-level tile structure is used to ...


Low-noise microwave f.e.t.s fabricated by molecular-beam epitaxy

S. G. Bandy Electronics Letters, 1979

The growth of m.b.e. GaAs suitable for f.e.t. fabrication is reported. The m.b.e. structure consists of an n+ = 2.5×1018 cm¿3 contact layer on top of an n+ = 3.5×1017 cm¿3 active layer. Using this material, f.e.t.s. have been fabricated that have a minimum noise figure of 1.5 dB with an associated gain of 15 dB at 8 GHz. These ...


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Educational Resources on Transistors

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eLearning

15th Annual NEC to have 28 technical sessions, 260 exhibits

Electrical Engineering, 1959

None


A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters

Michael Pehl; Tobias Massier; Helmut Graeb; Ulf Schlichtmann 2008 IEEE International Conference on Computer Design, 2008

Many methods for analog circuit sizing are available as commercial, in-house and academic tools. They are based on continuous optimization, e.g., of transistor geometries, although the subsequent layout step requires values on a pre-defined grid. In addition, sizing of transistors for bipolar and RF circuits frequently necessitates the use of multiples of predefined values for the design parameters. This paper ...


Comparison of DI and JI lateral IGBTs

Y. S. Huang; B. J. Baliga; S. Tandon; A. Reisman Proceedings of the 4th International Symposium on Power Semiconductor Devices and Ics, 1992

First Page of the Article ![](/xploreAssets/images/absImages/00991234.png)


Buffer allocation algorithm with consideration of routing congestion

Yuchun Ma; Xianiong Hong; Sheqin Dong; Song Chen; Yici Cai; Chung-Kuan Cheng; Jun Gu ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 2004

The dominating contribution of interconnect to system performance has made it critical to plan the buffers and the routes resource in the early stage of the layout. In this paper, we present a congestion estimation model which takes the buffer insertion sites into consideration. Based on the feasible region of the buffer insertion, the two-level tile structure is used to ...


Low-noise microwave f.e.t.s fabricated by molecular-beam epitaxy

S. G. Bandy Electronics Letters, 1979

The growth of m.b.e. GaAs suitable for f.e.t. fabrication is reported. The m.b.e. structure consists of an n+ = 2.5×1018 cm¿3 contact layer on top of an n+ = 3.5×1017 cm¿3 active layer. Using this material, f.e.t.s. have been fabricated that have a minimum noise figure of 1.5 dB with an associated gain of 15 dB at 8 GHz. These ...


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IEEE-USA E-Books

  • No title

    Ever since its invention in the 1980s, the compound semiconductor heterojunction-based high electron mobility transistor (HEMT) has been widely used in radio frequency (RF) applications. This book provides readers with broad coverage on techniques and new trends of HEMT, employing leading compound semiconductors, III-N and III-V materials. The content includes an overview of GaN HEMT device-scaling technologies and experimental research breakthroughs in fabricating various GaN MOSHEMT transistors. Readers are offered an inspiring example of monolithic integration of HEMT with LEDs, too. The authors compile the most relevant aspects of III-V HEMT, including the current status of state-of-art HEMTs, their possibility of replacing the Si CMOS transistor channel, and growth opportunities of III-V materials on an Si substrate. With detailed exploration and explanations, the book is a helpful source suitable for anyone learning about and working on compound semiconductor devices.

  • Performance Prospects of Subthreshold Logic Circuits

    The possibility of lowering the dissipation energy is addressed for the following conventional device technologies: multithreshold circuits, power management and subthreshold logic. In a multithreshold circuit, designers can assume that different circuit blocks can have different threshold voltages. They can set low threshold voltages for high???speed circuit blocks and high threshold voltages for low???power circuit blocks. This technique is widely applied to commercial integrated circuits (ICs). Circuit designers initially used multithreshold devices and power management to reduce the dissipation power of ICs. Reducing dissipation power by lowering the supply voltage is also a conventional design guideline, where metal oxide semiconductor field???effect transistors (MOSFETs) are used in the conventional manner in the circuit. On the other hand, the subthreshold logic and near???subthreshold logic approaches are quite different from the design idea of focusing on ???ON??? state performance. Circuit designers are now paying close attention to the quasi??????OFF??? state.

  • A ISOMHz Direct Digital Frequency Synthesizer in 1.25m CMOS with 90dBc Spurious Performance

    A monolithic CMOS direct digital frequency synthesizer (DDFS) is presented which synthesizes a 12-b output sine wave at 150 Msamples/s, This sine wave Is spectrally pure to -90.3 dBc over the entire tuning bandwidth. Phase noise of the output sine wave is equivalent to or better than that of the ISO-MHz reference clock. The synthesizer covers a bandwidth from dc to 7S MHz in steps of 0.035 Hz with a switching speed of 6.7 ns and a tuning latency of 13 clock cycles. An efficient look-up table method for calculating the sine function is used, which reduces ROM storage requirements by a factor of 128:1. All circuit designs are fully static and are tolerant to transistor threshold shifts caused by radiation or process variations. The DDFS is fabricated in a 1.25-m radiation-hardened double-level metal bulk P-well CMOS process which is tolerant to over 106 rd(Si) of total dose radiation. The die size is 195 mil x195 mil with a device count of 35000 transistors. Power dissipation is 950 mW at a clock rate of 100 MHz.

  • Overview

    This chapter describes the fundamentals of metal oxide semiconductor (MOS) device physics. It discusses the physics of bulk metal oxide semiconductor field???effect transistors (MOSFETs). The chapter introduces some important physics related to silicon???on???insulator metal oxide semiconductor field???effect transistors (SOI MOSFETs) and explores the theoretical basis of tunnel field???effect transistors (TFETs). It is obvious that we must minimize the subthreshold swing (SS) value of the MOS device in designing device parameters for low???power applications. However, there is still some controversy regarding the issue of whether the subthreshold issue is the substantial problem in overcoming the stand???by power issue. In many MOS devices, there is a simultaneous increase in the band???to???band tunneling (BTBT) current around the source and drain junctions because there must be shallow junctions in bulk devices or an extremely thin semiconductor layer in silicon???on???insulator (SOI) devices in order to suppress short???channel effects.

  • Scrolled Si/SiGe Heterostructures as Building Blocks for TubeLike FieldEffect Transistors

    This chapter contains sections titled: Introduction Charge carrier density in modulation doped scrolled Si/Si1-xGex structures Low-field hole mobility in rolled-up Si/SiGe structures Conclusions

  • Supplementary Study on Buried Oxide Characterization:

    This chapter proposes a macroscopic physical model for the buried oxide having a transition layer in a SIMOX substrate to estimate the parasitic capacitance. The Clausius-Mossotti relationship for two media is introduced into the model, employing an empirical factor to match with a high-frequency response. Peaks in the capacitance dependence on frequency appear only in devices with the buried oxide having a transition layer. This property can be explained by the proposed model. It is also shown that the transition layer adjacent to buried oxide should be eliminated to reduce parasitic capacitance. [©1992 IEEE. Reprinted, with permission, from Y. Omura and K. Izumi, A macroscopic physical model and capacitive response of the buried oxide having a transition layer in a SIMOX substrate, IEEE Transactions on Electron Devices, vol. 39, pp. 1916-1921, 1992.]

  • HighTemperature PointContact Transistors and Schottky Diodes Formed on Synthetic BoronDoped Diamond

    Point-contact transistors and Schottky diodes have been formed on synthetic boron-doped diamond. This is the FIRST report of diamond transistors that have power gain. Further. the transistors exhibited power gain at 510°C and the Schottky diodes were operational at 700°C.

  • Front Matter

    The prelims comprise: Half-Title Page Title Page Copyright Page Contents Preface Acknowledgements Introduction to an Exotic Device World

  • Gate Field Engineering and Source/Drain Diffusion Engineering for High???Performance Si Wire Gate???All???Around MOSFET and Low???Power Strategy in a Sub???30 nm???Channel Regime

    This chapter reconsiders the design methodology of the short???channel gate???all???around (GAA) silicon???on???insulator (SOI) MOSFET and proposes an advanced concept that offers enhanced performance. The new ideas raised here are based on gate field engineering and source and drain diffusion engineering. The validity of the proposal is demonstrated by device simulations. Covering the junction of a Si wire body with a relatively thick gate insulator raises the carrier density of low???doped source and drain diffusion regions, resulting in a drastic reduction in parasitic resistance (which has, up to now, hindered performance enhancement) as well as the suppression of short???channel effects due to the effective extension of channel length; it is also demonstrated that these advantages can be expected even for a narrow, highly doped source and drain diffusion regions with abrupt junctions. The simulation results suggest that 15 and 20 nm channel gate???all???around silicon???on???insulator metal oxide semiconductor field???effect transistors (GAA SOI MOSFETs) with the abrupt junction will be promising if the devices have a body cross???section of 10???nm????????10 nm and a thick insulator covers the junction. On the other hand, as it has been demonstrated that the proposed GAA device must have long and graduated source and drain diffusion regions in order to achieve the expected one???order???lower standby power consumption, a loss of drivability has to be accepted. However, it is shown that drivability can be improved by slightly expanding the cross???section of source and drain diffusion regions without seriously impacting the area penalty.

  • Demand for High???Performance SOI Devices

    This chapter discusses that silicon???on???insulator (SOI) devices would continue to contribute to high???speed device technology because most demands from industry were expressed simply as ???high???speed digital signal processing???. Recently, however, the issue of energy consumption has become an international concern. Global warming, energy harvesting, and sensor networks for various social risks are pushing demands for lower energy consumption in every country. As a large part of this demand can be satisfied by electronics based technology, several innovations are being targeted. It is clear that SOI device technology can contribute to greater power savings. Actually, SOI devices are promising low???power devices when the device architecture is optimized for each application. The chapter also addresses how the fully depleted SOI metal oxide semiconductor field???effect transistor (MOSFET), and multigate SOI devices including Fin field???effect transistors (FinFETs) and gate???all???around (GAA) MOSFETs, can contribute to low???energy device technologies.



Standards related to Transistors

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IEEE Standard for Test Methods for the Characterization of Organic Transistors and Materials

This standard describes a method for characterizing organic electronic devices, including measurement techniques, methods of reporting data, and the testing conditions during characterization.


Standard for Test Methods for the Characterization of Organic Transistor-Based Ring Oscillators

This is a full-use standard that specifies methods for the characterization of organic transistor-based ring oscillators. The methods are applicable to all ring oscillators fabricated from organic semiconductor materials and are independent of the fabrication process.



Jobs related to Transistors

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