Microprocessor

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A microprocessor incorporates the functions of a computer's central processing unit (CPU) on a single integrated circuit (IC, or microchip). It is a multipurpose, programmable, clock-driven, register-based electronic device that accepts binary data as input, processes it according to instructions stored in its memory, and provides results as output. (Wikipedia.org)






Conferences related to Microprocessor

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2018 IEEE Symposium on VLSI Circuits

Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2020 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2016 IEEE Symposium on VLSI Circuits

    circuit design to address challenges of deeply scaled technologies - e.g. dfm, variability, reliability - digital circuit techniques - analog and mixed signal circuits such as data converters and amp

  • 2014 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2012 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation

  • 2011 Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2010 IEEE Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies - Adaptive pow

  • 2009 Symposium on VLSI Circuits

    Circuit design to address challenges of deeply scaled technologies - e.g. DFM, variability, reliability - Digital circuit techniques - Analog and mixed signal circuits such as data converters and amplifiers to address performance, power, technology scaling, and variability - Complex SOC systems describing new architectures and implementations - Circuit approaches for clock generation and distribution - Advances in memory circuits; especially for embedded memories in scaled technologies

  • 2008 IEEE Symposium on VLSI Circuits

  • 2007 IEEE Symposium on VLSI Circuits


2017 IEEE International Solid- State Circuits Conference - (ISSCC)

The International Solid-State Circuits Conference is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS IC's.


2014 IEEE Custom Integrated Circuits Conference - CICC 2014

The IEEE Custom Integrated Circuits Conference (CICC) is the premier conference devoted to IC development. CICC showcases original, first-published innovative analog and digital circuit techniques covering a broad spectrum of technical topics. It is a forum for circuit, IC and SoC designers, CAD developers, manufacturers and ASIC users. CICC is the conference to find out how to solve design problems and improve circuit design and chip design techniques.


ESSCIRC 2013 - 39th European Solid State Circuits Conference

The aim of the ESSCIRC conference is to provide an annual European forum for the presentation and discussion of recent advances in solid-state circuits and technologies. The conference is jointly organized with ESSDERC, which covers advances in process technology and devices.

  • ESSCIRC 2012 - 38th European Solid State Circuits Conference

    The aim of the ESSCIRC conference is to provide an annual European forum for the presentation and discussion of recent advances in solid-state circuits.

  • ESSCIRC 2011 - 37th European Solid State Circuits Conference

    he aim of the ESSCIRC conference is to provide an annual European forum for the presentation and discussion of recent advances in solid-state circuits. ESSCIRC and its sister conference ESSDERC, which deals with solid-state devices and technologies, are jointly organized.

  • ESSCIRC 2010 - 36th European Solid State Circuits Conference

    The aim of the ESSCIRC conference is to provide an annual European forum for the presentation and discussion of recent advances in solid-state circuits.

  • ESSCIRC 2009 - 35th European Solid State Circuits Conference

    The aim of the ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and technologies. The aim of the ESSCIRC is to provide corresponding forum in the field of silicon design and implementation.


2012 16th IEEE International Symposium on Power Line Communications and Its Applications (ISPLC)

ISPLC 2012 will bring together academia and industry professionals as well as students and researchers to present and discuss ongoing work on existing and future power line communication (PLC) systems, PLC applications, PLC standardization activities. The contributions presented at ISPLC will span all aspects of communications over power lines, including access, home networking, in-vehicle applications, utility applications, smart grids, and more.


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Periodicals related to Microprocessor

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Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Instrumentation and Measurement, IEEE Transactions on

Measurements and instrumentation utilizing electrical and electronic techniques.


Micro, IEEE

IEEE Micro magazine presents high-quality technical articles from designers, systems integrators, and users discussing the design, performance, or application of microcomputer and microprocessor systems. Topics include architecture, components, subassemblies, operating systems, application software, communications, fault tolerance, instrumentation, control equipment, and peripherals.


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Most published Xplore authors for Microprocessor

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Xplore Articles related to Microprocessor

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On the need for common evaluation methods for fault tolerance costs in microprocessors

P. Michele; L. Regis 11th IEEE International On-Line Testing Symposium, 2005

Technological evolution is making fault tolerance more and more important in all application fields and it is therefore mandatory to have good strategies to measure its impact on existing systems. A lot of work has been done on fault characterization and modelling, but confusion still abounds when coming to performance loss evaluation. This is especially true for microprocessors, where "performance" ...


Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

Jaehyun Park; Donghwa Shin; Naehyuck Chang; Massoud Pedram 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 2010

Dynamic voltage and frequency scaling (DVS) has been studied for well over a decade, and even commercial systems widely support DVS nowadays. Nevertheless, existing DVS transition overhead models do not accurately reflect modern DVS architectures including modern DC-DC converters, PLL (Phase Lock Loop), and voltage and frequency change policies. Incorrect DVS overhead models prevent one from achieving the maximum energy ...


A discrete time variable structure controller for a brushless DC motor drive

K. -W. Lim; T. -S. Low; M. F. Rahman; L. -B. Wee IEEE Transactions on Industrial Electronics, 1991

The design and the microprocessor-based implementation of a variable- structure-strategy (VSS) controller for a brushless DC motor drive are described. The controller is a conventional variable-structure design in the continuous-time domain. However, the microprocessor implementation using a constant sample period implies that full sliding mode is not achieved. The properties of the quasi-sliding that results are explored. It is shown ...


Instruction flow-based front-end throttling for power-aware high-performance processors

A. Baniasadi; A. Moshovos Low Power Electronics and Design, International Symposium on, 2001., 2001

We present a number of power-aware instruction front-end (fetch/decode) throttling methods for high-performance dynamically-scheduled superscalar processors. Our methods reduce power dissipation by selectively turning on and off instruction fetch and decode. Moreover, they have a negligible impact on performance as they deliver instructions just in time for exploiting the available parallelism. Previously proposed front-end throttling methods rely on branch prediction ...


Evaluation and improvements of programming models for the Intel SCC many-core processor

Carsten Clauss; Stefan Lankes; Pablo Reble; Thomas Bemmerl 2011 International Conference on High Performance Computing & Simulation, 2011

Since the beginning of the multicore era, parallel processing has become prevalent across the board. On a traditional multicore system, a single operating system manages all cores and schedules threads and processes among them, inherently supported by hardware-implemented cache coherence protocols. However, a further growth of the number of cores per system implies an increasing chip complexity, especially with respect ...


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Educational Resources on Microprocessor

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eLearning

On the need for common evaluation methods for fault tolerance costs in microprocessors

P. Michele; L. Regis 11th IEEE International On-Line Testing Symposium, 2005

Technological evolution is making fault tolerance more and more important in all application fields and it is therefore mandatory to have good strategies to measure its impact on existing systems. A lot of work has been done on fault characterization and modelling, but confusion still abounds when coming to performance loss evaluation. This is especially true for microprocessors, where "performance" ...


Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

Jaehyun Park; Donghwa Shin; Naehyuck Chang; Massoud Pedram 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 2010

Dynamic voltage and frequency scaling (DVS) has been studied for well over a decade, and even commercial systems widely support DVS nowadays. Nevertheless, existing DVS transition overhead models do not accurately reflect modern DVS architectures including modern DC-DC converters, PLL (Phase Lock Loop), and voltage and frequency change policies. Incorrect DVS overhead models prevent one from achieving the maximum energy ...


A discrete time variable structure controller for a brushless DC motor drive

K. -W. Lim; T. -S. Low; M. F. Rahman; L. -B. Wee IEEE Transactions on Industrial Electronics, 1991

The design and the microprocessor-based implementation of a variable- structure-strategy (VSS) controller for a brushless DC motor drive are described. The controller is a conventional variable-structure design in the continuous-time domain. However, the microprocessor implementation using a constant sample period implies that full sliding mode is not achieved. The properties of the quasi-sliding that results are explored. It is shown ...


Instruction flow-based front-end throttling for power-aware high-performance processors

A. Baniasadi; A. Moshovos Low Power Electronics and Design, International Symposium on, 2001., 2001

We present a number of power-aware instruction front-end (fetch/decode) throttling methods for high-performance dynamically-scheduled superscalar processors. Our methods reduce power dissipation by selectively turning on and off instruction fetch and decode. Moreover, they have a negligible impact on performance as they deliver instructions just in time for exploiting the available parallelism. Previously proposed front-end throttling methods rely on branch prediction ...


Evaluation and improvements of programming models for the Intel SCC many-core processor

Carsten Clauss; Stefan Lankes; Pablo Reble; Thomas Bemmerl 2011 International Conference on High Performance Computing & Simulation, 2011

Since the beginning of the multicore era, parallel processing has become prevalent across the board. On a traditional multicore system, a single operating system manages all cores and schedules threads and processes among them, inherently supported by hardware-implemented cache coherence protocols. However, a further growth of the number of cores per system implies an increasing chip complexity, especially with respect ...


More eLearning Resources

IEEE-USA E-Books

  • Technology Issues

    This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

  • CMOS Scaling and Issues in Sub0.25 m Systems

    This chapter contains sections titled: MOSFET Scaling Theory CMOS Scaling Issues below 0.25 ?>m Interconnect RC Delay Low-Temperature CMOS This chapter contains sections titled: References

  • Techniques for Leakage Power Reduction

    This chapter contains sections titled: Introduction Transistor Leakage Current Components Circuit Subthreshold Leakage Current Leakage Control Techniques This chapter contains sections titled: Acknowledgments References

  • Techniques for Driving Interconnect

    This chapter contains sections titled: Introduction Technology Scaling Trends Problems and Solutions Regarding Capacitance Problems and Solutions Regarding Inductance Problems and Solutions Regarding Resistance Problems and Solutions Regarding Long Distance Routing Conclusion This chapter contains sections titled: Acknowledgments References

  • LowVoltage Technologies

    This chapter contains sections titled: Low-Voltage Low-Threshold-Voltage Circuit Design Power-Down Scheme Controlling _V_ TH through Substrate Bias Processor Design Examples Conclusion This chapter contains sections titled: References

  • Unit Protection Systems

    This chapter contains sections titled: Overlapping the Zones of Protection Importance of Differential Systems for Arc Flash Reduction Bus Differential Schemes High Impedance Differential Relays Low Impedance Current Differential Relays Electromechanical Transformer Differential Relays Microprocessor-Based Transformer Differential Relays Pilot Wire Protection Modern Line Current Differential Protection Examples of Arc Flash Reduction with Differential Relays Review Questions References

  • No title

    The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.

  • I/O and ESD Circuit Design

    This chapter contains sections titled: Introduction Power Supply Considerations Off-Chip-Driver Edge Rate Control Mixed-Voltage I/O Impedance Matching Precompensation Drivers Input Receivers The ESD Threat ESD Models Circuit Topology of the ESD Protection Network ESD Protection Design Elements and Methods Power Supply Clamps CDM Considerations This chapter contains sections titled: References

  • Soi Technology and Circuits

    This chapter contains sections titled: Introduction Device Design Considerations for PD SOI versus FD SOI Device Results PD - SOI CMOS Digital Circuits SOI for Low Power Conclusion This chapter contains sections titled: References

  • No title

    Having hit power limitations to even more aggressive out-of-order execution in processor cores, many architects in the past decade have turned to single- instruction-multiple-data (SIMD) execution to increase single-threaded performance. SIMD execution, or having a single instruction drive execution of an identical operation on multiple data items, was already well established as a technique to efficiently exploit data parallelism. Furthermore, support for it was already included in many commodity processors. However, in the past decade, SIMD execution has seen a dramatic increase in the set of applications using it, which has motivated big improvements in hardware support in mainstream microprocessors. The easiest way to provide a big performance boost to SIMD hardware is to make it wider-- i.e., increase the number of data items hardware operates on simultaneously. Indeed, microprocessor vendors have done this. However, as we exploit more data parallelism in applications, cert in challenges can negatively impact performance. In particular, conditional execution, noncontiguous memory accesses, and the presence of some dependences across data items are key roadblocks to achieving peak performance with SIMD execution. This book first describes data parallelism, and why it is so common in popular applications. We then describe SIMD execution, and explain where its performance and energy benefits come from compared to other techniques to exploit parallelism. Finally, we describe SIMD hardware support in current commodity microprocessors. This includes both expected design tradeoffs, as well as unexpected ones, as we work to overcome challenges encountered when trying to map real software to SIMD execution.



Standards related to Microprocessor

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IEEE Recommended Practice for Microprocessor-Based Protection Equipment Firmware Control

The scope of this recommended practice is to identify the means for timely and efficient exchange of information between manufacturers and users of protection-related equipment with respect to (1) changes in device firmware and (2) the impact of those changes. It will also include an examination of the technical and operational ramifications resulting from changes in the device firmware. Only ...


IEEE Standard for a 32-bit Microprocessor Architecture


IEEE Standard for a Versatile Backplane Bus: VMEbus


IEEE Standard for an 8-Bit Microcomputer Bus System: STD Bus


IEEE Standard for Mechanical Core Specifications for Microprocessors



Jobs related to Microprocessor

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